diff mbox series

powerpc/vdso: Fix __kernel_sync_dicache sequence with coherent icache

Message ID 20220520123649.258440-1-npiggin@gmail.com (mailing list archive)
State Accepted
Headers show
Series powerpc/vdso: Fix __kernel_sync_dicache sequence with coherent icache | expand

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Commit Message

Nicholas Piggin May 20, 2022, 12:36 p.m. UTC
Processors with coherent icache require the sequence sync ; icbi ; isync
to entire store->execute coherency. icbi (to any address) must be
executed to ensure isync flushes the pipeline. See "POWER9 Processor
User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)" for
details.

__kernel_sync_dicache is missing icbi for the coherent icache path.
Add it.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/kernel/vdso/cacheflush.S | 1 +
 1 file changed, 1 insertion(+)

Comments

Michael Ellerman July 29, 2022, 1:02 p.m. UTC | #1
On Fri, 20 May 2022 22:36:49 +1000, Nicholas Piggin wrote:
> Processors with coherent icache require the sequence sync ; icbi ; isync
> to entire store->execute coherency. icbi (to any address) must be
> executed to ensure isync flushes the pipeline. See "POWER9 Processor
> User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)" for
> details.
> 
> __kernel_sync_dicache is missing icbi for the coherent icache path.
> Add it.
> 
> [...]

Applied to powerpc/next.

[1/1] powerpc/vdso: Fix __kernel_sync_dicache sequence with coherent icache
      https://git.kernel.org/powerpc/c/28f07fab26319dacc5675ae01dfc84d82122c59b

cheers
diff mbox series

Patch

diff --git a/arch/powerpc/kernel/vdso/cacheflush.S b/arch/powerpc/kernel/vdso/cacheflush.S
index d4e43ab2d5df..0085ae464dac 100644
--- a/arch/powerpc/kernel/vdso/cacheflush.S
+++ b/arch/powerpc/kernel/vdso/cacheflush.S
@@ -91,6 +91,7 @@  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 3:
 	crclr	cr0*4+so
 	sync
+	icbi	0,r1
 	isync
 	li	r3,0
 	blr