[v2] powerpc: Update documentation of ISA versions for Power10

Update the CPU to ISA Version Mapping document to include Power10 and
ISA v3.1.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
v2: Transactional Memory = No
---
 Documentation/powerpc/isa-versions.rst | 4 ++++
 1 file changed, 4 insertions(+)

Le 27/08/2020 à 06:05, Jordan Niethe a écrit :
> Update the CPU to ISA Version Mapping document to include Power10 and
> ISA v3.1.

Maybe Documentation/powerpc/cpu_families.rst should be updated as well.

Christophe



> 
> Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> ---
> v2: Transactional Memory = No
> ---
>   Documentation/powerpc/isa-versions.rst | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/powerpc/isa-versions.rst b/Documentation/powerpc/isa-versions.rst
> index a363d8c1603c..3873bbba183a 100644
> --- a/Documentation/powerpc/isa-versions.rst
> +++ b/Documentation/powerpc/isa-versions.rst
> @@ -7,6 +7,7 @@ Mapping of some CPU versions to relevant ISA versions.
>   ========= ====================================================================
>   CPU       Architecture version
>   ========= ====================================================================
> +Power10   Power ISA v3.1
>   Power9    Power ISA v3.0B
>   Power8    Power ISA v2.07
>   Power7    Power ISA v2.06
> @@ -32,6 +33,7 @@ Key Features
>   ========== ==================
>   CPU        VMX (aka. Altivec)
>   ========== ==================
> +Power10    Yes
>   Power9     Yes
>   Power8     Yes
>   Power7     Yes
> @@ -47,6 +49,7 @@ PPC970     Yes
>   ========== ====
>   CPU        VSX
>   ========== ====
> +Power10    Yes
>   Power9     Yes
>   Power8     Yes
>   Power7     Yes
> @@ -62,6 +65,7 @@ PPC970     No
>   ========== ====================================
>   CPU        Transactional Memory
>   ========== ====================================
> +Power10    No  (* see Power ISA v3.1 Appendix A.)
>   Power9     Yes (* see transactional_memory.txt)
>   Power8     Yes
>   Power7     No
>

On Thu, Aug 27, 2020 at 2:49 PM Christophe Leroy
<christophe.leroy@csgroup.eu> wrote:
>
>
>
> Le 27/08/2020 à 06:05, Jordan Niethe a écrit :
> > Update the CPU to ISA Version Mapping document to include Power10 and
> > ISA v3.1.
>
> Maybe Documentation/powerpc/cpu_families.rst should be updated as well.
Good idea it still needs Power9 too.
>
> Christophe
>
>
>
> >
> > Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> > ---
> > v2: Transactional Memory = No
> > ---
> >   Documentation/powerpc/isa-versions.rst | 4 ++++
> >   1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/powerpc/isa-versions.rst b/Documentation/powerpc/isa-versions.rst
> > index a363d8c1603c..3873bbba183a 100644
> > --- a/Documentation/powerpc/isa-versions.rst
> > +++ b/Documentation/powerpc/isa-versions.rst
> > @@ -7,6 +7,7 @@ Mapping of some CPU versions to relevant ISA versions.
> >   ========= ====================================================================
> >   CPU       Architecture version
> >   ========= ====================================================================
> > +Power10   Power ISA v3.1
> >   Power9    Power ISA v3.0B
> >   Power8    Power ISA v2.07
> >   Power7    Power ISA v2.06
> > @@ -32,6 +33,7 @@ Key Features
> >   ========== ==================
> >   CPU        VMX (aka. Altivec)
> >   ========== ==================
> > +Power10    Yes
> >   Power9     Yes
> >   Power8     Yes
> >   Power7     Yes
> > @@ -47,6 +49,7 @@ PPC970     Yes
> >   ========== ====
> >   CPU        VSX
> >   ========== ====
> > +Power10    Yes
> >   Power9     Yes
> >   Power8     Yes
> >   Power7     Yes
> > @@ -62,6 +65,7 @@ PPC970     No
> >   ========== ====================================
> >   CPU        Transactional Memory
> >   ========== ====================================
> > +Power10    No  (* see Power ISA v3.1 Appendix A.)
> >   Power9     Yes (* see transactional_memory.txt)
> >   Power8     Yes
> >   Power7     No
> >

Jordan Niethe <jniethe5@gmail.com> writes:
> Update the CPU to ISA Version Mapping document to include Power10 and
> ISA v3.1.
>
> Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> ---
> v2: Transactional Memory = No
> ---
>  Documentation/powerpc/isa-versions.rst | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/powerpc/isa-versions.rst b/Documentation/powerpc/isa-versions.rst
> index a363d8c1603c..3873bbba183a 100644
> --- a/Documentation/powerpc/isa-versions.rst
> +++ b/Documentation/powerpc/isa-versions.rst
> @@ -62,6 +65,7 @@ PPC970     No
>  ========== ====================================
>  CPU        Transactional Memory
>  ========== ====================================
> +Power10    No  (* see Power ISA v3.1 Appendix A.)

There's three "Appendix A"s in ISA v3.1.

There's one in Book I, and one in Book II.

And then the one you're referring to is not actually in Book III, it's
listed after Book III, and is apparently an appendix to all three books?

Which is just utterly confusing.

So I'll change it to say:

"Appendix A. Notes on the Removal of Transactional Memory from the Architecture"

Which is very long, but at least you can search for it.

cheers

On Thu, 27 Aug 2020 14:05:56 +1000, Jordan Niethe wrote:
> Update the CPU to ISA Version Mapping document to include Power10 and
> ISA v3.1.

Applied to powerpc/next.

[1/1] powerpc: Update documentation of ISA versions for Power10
      https://git.kernel.org/powerpc/c/51a1588154cb1ddc4fe8fa786324dca398f1a458

cheers