| Message ID | 20191104023305.9581-2-alastair@au1.ibm.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 29430fae82073d39b1b881a3cd507416a56a363f |
| Headers | show |
| Series | powerpc: convert cache asm to C | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (b9ba205b97bda75388e4014914ae0bdc0022464c) |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 16 lines checked |
On Mon, Nov 04, 2019 at 01:32:53PM +1100, Alastair D'Silva wrote: > When calling flush_icache_range with a size >4GB, we were masking > off the upper 32 bits, so we would incorrectly flush a range smaller > than intended. > > This patch replaces the 32 bit shifts with 64 bit ones, so that > the full size is accounted for. Please send this separately, to be committed right now? It is a bug fix, independent of the rest of the series. Segher
Le 04/11/2019 à 20:43, Segher Boessenkool a écrit : > On Mon, Nov 04, 2019 at 01:32:53PM +1100, Alastair D'Silva wrote: >> When calling flush_icache_range with a size >4GB, we were masking >> off the upper 32 bits, so we would incorrectly flush a range smaller >> than intended. >> >> This patch replaces the 32 bit shifts with 64 bit ones, so that >> the full size is accounted for. > > Please send this separately, to be committed right now? It is a bug fix, > independent of the rest of the series. > Patch 4/6 needs it, as it drops the function. Or do you mean that the series should drop the assembly at once, and this patch should only go into stable ? But I guess mpe can take this patch alone if he wants to ? By the way, Patch 2/6 is also a bugfix. Christophe
On Tue, Nov 05, 2019 at 07:04:04AM +0100, Christophe Leroy wrote: > Le 04/11/2019 à 20:43, Segher Boessenkool a écrit : > >Please send this separately, to be committed right now? It is a bug fix, > >independent of the rest of the series. > > Patch 4/6 needs it, as it drops the function. > > Or do you mean that the series should drop the assembly at once, and > this patch should only go into stable ? I meant that you can say these patches (yes, 2/ as well) are bug fixes, independent of the rest, and they can be picked up immediately, there is no need to wait for v18 of this series. > But I guess mpe can take this patch alone if he wants to ? Yeah, but you can help him do that ;-) Segher
On Mon, 2019-11-04 at 02:32:53 UTC, "Alastair D'Silva" wrote: > From: Alastair D'Silva <alastair@d-silva.org> > > When calling flush_icache_range with a size >4GB, we were masking > off the upper 32 bits, so we would incorrectly flush a range smaller > than intended. > > This patch replaces the 32 bit shifts with 64 bit ones, so that > the full size is accounted for. > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > Cc: stable@vger.kernel.org Series applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/29430fae82073d39b1b881a3cd507416a56a363f cheers
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index b55a7b4cb543..9bc0aa9aeb65 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */ - srw. r8,r8,r9 /* compute line count */ + srd. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 1: dcbst 0,r6 @@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) subf r8,r6,r4 /* compute length */ add r8,r8,r5 lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */ - srw. r8,r8,r9 /* compute line count */ + srd. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 2: icbi 0,r6