| Message ID | 20170227033241.GA3591@fergus.ozlabs.ibm.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
On Mon, 2017-02-27 at 03:32:41 UTC, Paul Mackerras wrote: > The POWER9 MMU reads and caches entries from the process table. > When we kexec from one kernel to another, the second kernel sets > its process table pointer but doesn't currently do anything to > make the CPU invalidate any cached entries from the old process table. > This adds a tlbie (TLB invalidate entry) instruction with parameters > to invalidate caching of the process table after the new process > table is installed. > > Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/7a70d7288c926ae88e0c773fbb506a cheers
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c index 7ac17e9..c6a9f37 100644 --- a/arch/powerpc/mm/pgtable-radix.c +++ b/arch/powerpc/mm/pgtable-radix.c @@ -173,6 +173,10 @@ static void __init radix_init_pgtable(void) */ register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12); pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd); + asm volatile("ptesync" : : : "memory"); + asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : : + "r" (TLBIEL_INVAL_SET_LPID), "r" (0)); + asm volatile("eieio; tlbsync; ptesync" : : : "memory"); } static void __init radix_init_partition_table(void)
The POWER9 MMU reads and caches entries from the process table. When we kexec from one kernel to another, the second kernel sets its process table pointer but doesn't currently do anything to make the CPU invalidate any cached entries from the old process table. This adds a tlbie (TLB invalidate entry) instruction with parameters to invalidate caching of the process table after the new process table is installed. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> --- arch/powerpc/mm/pgtable-radix.c | 4 ++++ 1 file changed, 4 insertions(+)