Message ID | 1608022578-1532-1-git-send-email-atrajeev@linux.vnet.ibm.com (mailing list archive) |
---|---|
State | Accepted |
Commit | ef0e3b650f8ddc54bb70868852f50642ee3ae765 |
Headers | show |
Series | [V3] powerpc/perf: Fix Threshold Event Counter Multiplier width for P10 | expand |
On Tue, 15 Dec 2020 03:56:18 -0500, Athira Rajeev wrote: > Threshold Event Counter Multiplier (TECM) is part of Monitor Mode > Control Register A (MMCRA). This field along with Threshold Event > Counter Exponent (TECE) is used to get threshould counter value. > In Power10, this is a 8bit field, so patch fixes the > current code to modify the MMCRA[TECM] extraction macro to > handle this change. ISA v3.1 says this is a 7 bit field but > POWER10 it's actually 8 bits which will hopefully be fixed > in ISA v3.1 update. Applied to powerpc/next. [1/1] powerpc/perf: Fix Threshold Event Counter Multiplier width for P10 https://git.kernel.org/powerpc/c/ef0e3b650f8ddc54bb70868852f50642ee3ae765 cheers
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c index 24f0a90..6ab5b27 100644 --- a/arch/powerpc/perf/isa207-common.c +++ b/arch/powerpc/perf/isa207-common.c @@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight) u64 sier = mfspr(SPRN_SIER); u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; + if (cpu_has_feature(CPU_FTR_ARCH_31)) + mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); + if (val == 0 || val == 7) *weight = 0; else diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index 4208764..454b32c 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -231,6 +231,10 @@ #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\ MMCRA_THR_CTR_EXP_MASK) +#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul +#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\ + P10_MMCRA_THR_CTR_MANT_MASK) + /* MMCRA Threshold Compare bit constant for power9 */ #define p9_MMCRA_THR_CMP_SHIFT 45