| Message ID | 1584121747-6213-1-git-send-email-atrajeev@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] powerpc/perf: Use SIER_USER_MASK while updating SPRN_SIER for EBB events | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (ab326587bb5fb91cc97df9b9f48e9e1469f04621) |
| snowpatch_ozlabs/build-ppc64le | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64be | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64e | success | Build succeeded |
| snowpatch_ozlabs/build-pmac32 | success | Build succeeded |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 8 lines checked |
| snowpatch_ozlabs/needsstable | warning | Please consider tagging this patch for stable! |
On Fri, Mar 13, 2020 at 01:49:07PM -0400, Athira Rajeev wrote:
> Sampled instruction address register (SIER), is a PMU register,
SIER stands for "Sampled Instruction Event Register", instead. With that
change, your patch is totally clear :-)
Segher
> On 13-Mar-2020, at 11:36 PM, Segher Boessenkool <segher@kernel.crashing.org> wrote: > > On Fri, Mar 13, 2020 at 01:49:07PM -0400, Athira Rajeev wrote: >> Sampled instruction address register (SIER), is a PMU register, > > SIER stands for "Sampled Instruction Event Register", instead. With that > change, your patch is totally clear :-) > Hi Segher, Thanks for reviewing. My bad. I am sending a V3 with the register name corrected in the commit message. Athira > > Segher
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 3086055..48b61cc 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -579,7 +579,7 @@ static void ebb_switch_out(unsigned long mmcr0) return; current->thread.siar = mfspr(SPRN_SIAR); - current->thread.sier = mfspr(SPRN_SIER); + current->thread.sier = mfspr(SPRN_SIER) & SIER_USER_MASK; current->thread.sdar = mfspr(SPRN_SDAR); current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
Sampled instruction address register (SIER), is a PMU register, captures architecture state for a given sample. And sier_user_mask defined in commit 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit book3s") defines the architected bits that needs to be saved from the SPR. Currently all of the bits from SIER are saved for EBB events. Patch fixes this by ANDing the "sier_user_mask" to data from SIER in ebb_switch_out(). This will force save only architected bits from the SIER. Fixes: 330a1eb7775b ("powerpc/perf: Core EBB support for 64-bit book3s") Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> --- Changes in v2: - Make the commit message more clearer. arch/powerpc/perf/core-book3s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)