| Message ID | 1379119755-21025-9-git-send-email-sukadev@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote: > On Power7, the DCACHE_SRC field in MMCRA register identifies the memory > hierarchy level (eg: L2, L3 etc) from which a data-cache miss for a > marked instruction was satisfied. > > Use the 'perf_mem_data_src' object to export this hierarchy level to user > space. Some memory hierarchy levels in Power7 don't map into the arch-neutral > levels. However, since newer generation of the processor (i.e. Power8) uses > fewer levels than in Power7, we don't really need to define new hierarchy > levels just for Power7. > > We instead, map as many levels as possible and approximate the rest. See > comments near dcache-src_map[] in the patch. > > Usage: > > perf record -d -e 'cpu/PM_MRK_GRP_CMPL/' <application> > perf report -n --mem-mode --sort=mem,sym,dso,symbol_daddr,dso_daddr" > > For samples involving load/store instructions, the memory > hierarchy level is shown as "L1 hit", "Remote RAM hit" etc. > # or > > perf record --data <application> > perf report -D > > Sample records contain a 'data_src' field which encodes the > memory hierarchy level: Eg: data_src 0x442 indicates > MEM_OP_LOAD, MEM_LVL_HIT, MEM_LVL_L2 (i.e load hit L2). Successfully built and boot tested this entire patchset both on a P7 and P8 system. Running some sample tests with ebizzy micro benchmark. Till now got only 0x142 and 0x0 values for data_src object for the sample records. Will experiment around bit more on P7 and P8 systems and post the results. Regards Anshuman
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote: > +static void power7_get_mem_data_src(union perf_mem_data_src *dsrc, > + struct pt_regs *regs) > +{ > + u64 idx; > + u64 mmcra = regs->dsisr; > + u64 addr; > + int ret; > + unsigned int instr; > + > + if (mmcra & POWER7_MMCRA_DCACHE_MISS) { > + idx = mmcra & POWER7_MMCRA_DCACHE_SRC_MASK; > + idx >>= POWER7_MMCRA_DCACHE_SRC_SHIFT; > + > + dsrc->val |= dcache_src_map[idx]; > + return; > + } > + > + instr = 0; > + addr = perf_instruction_pointer(regs); > + > + if (is_kernel_addr(addr)) > + instr = *(unsigned int *)addr; > + else { > + pagefault_disable(); > + ret = __get_user_inatomic(instr, (unsigned int __user *)addr); > + pagefault_enable(); > + if (ret) > + instr = 0; > + } > + if (instr && instr_is_load_store(&instr)) Wondering if there is any possibility of getting positive values for "(mmcra & POWER7_MMCRA_DCACHE_SRC_MASK) >> POWER7_MMCRA_DCACHE_SRC_SHIFT" when the marked instruction did not have MMCRA[POWER7_MMCRA_DCACHE_MISS] bit set. In that case we should actually compute dsrc->val as in the previous case. I did couple of experiments on a P7 box, but was not able to find a instance for a marked instruction whose MMCRA[POWER7_MMCRA_DCACHE_MISS] bit not set and have a positive value POWER7_MMCRA_DCACHE_SRC field.
Anshuman Khandual [khandual@linux.vnet.ibm.com] wrote:
| On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
| > +static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
| > + struct pt_regs *regs)
| > +{
| > + u64 idx;
| > + u64 mmcra = regs->dsisr;
| > + u64 addr;
| > + int ret;
| > + unsigned int instr;
| > +
| > + if (mmcra & POWER7_MMCRA_DCACHE_MISS) {
| > + idx = mmcra & POWER7_MMCRA_DCACHE_SRC_MASK;
| > + idx >>= POWER7_MMCRA_DCACHE_SRC_SHIFT;
| > +
| > + dsrc->val |= dcache_src_map[idx];
| > + return;
| > + }
| > +
| > + instr = 0;
| > + addr = perf_instruction_pointer(regs);
| > +
| > + if (is_kernel_addr(addr))
| > + instr = *(unsigned int *)addr;
| > + else {
| > + pagefault_disable();
| > + ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
| > + pagefault_enable();
| > + if (ret)
| > + instr = 0;
| > + }
| > + if (instr && instr_is_load_store(&instr))
|
|
| Wondering if there is any possibility of getting positive values for
| "(mmcra & POWER7_MMCRA_DCACHE_SRC_MASK) >> POWER7_MMCRA_DCACHE_SRC_SHIFT"
| when the marked instruction did not have MMCRA[POWER7_MMCRA_DCACHE_MISS]
| bit set. In that case we should actually compute dsrc->val as in the previous
| case. I did couple of experiments on a P7 box, but was not able to find a
| instance for a marked instruction whose MMCRA[POWER7_MMCRA_DCACHE_MISS] bit
| not set and have a positive value POWER7_MMCRA_DCACHE_SRC field.
Confirmed again with the hardware team that if there was no DCACHE_MISS,
the DCACHE_SRC field will be clear.
Thanks,
Sukadev
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c index 56c67bc..ddfa548 100644 --- a/arch/powerpc/perf/power7-pmu.c +++ b/arch/powerpc/perf/power7-pmu.c @@ -11,8 +11,10 @@ #include <linux/kernel.h> #include <linux/perf_event.h> #include <linux/string.h> +#include <linux/uaccess.h> #include <asm/reg.h> #include <asm/cputable.h> +#include <asm/code-patching.h> /* * Bits in event code for POWER7 @@ -317,6 +319,97 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); } +#define POWER7_MMCRA_DCACHE_MISS (0x1LL << 55) +#define POWER7_MMCRA_DCACHE_SRC_SHIFT 51 +#define POWER7_MMCRA_DCACHE_SRC_MASK (0xFLL << POWER7_MMCRA_DCACHE_SRC_SHIFT) + +#define P(a, b) PERF_MEM_S(a, b) +#define PLH(a, b) (P(OP, LOAD) | P(LVL, HIT) | P(a, b)) +/* + * Map the Power7 DCACHE_SRC field (bits 9..12) in MMCRA register to the + * architecture-neutral memory hierarchy levels. For the levels in Power7 + * that don't map to the arch-neutral levels, approximate to nearest + * level. + * + * 1-hop: indicates another core on the same chip (2.1 and 3.1 levels). + * 2-hops: indicates a different chip on same or different node (remote + * and distant levels). + * + * For consistency with this interpretation of the hops, we dont use + * the REM_RAM1 level below. + * + * The *SHR and *MOD states of the cache are ignored/not exported to user. + * + * ### Levels marked with ### in comments below are approximated + */ +static u64 dcache_src_map[] = { + PLH(LVL, L2), /* 00: FROM_L2 */ + PLH(LVL, L3), /* 01: FROM_L3 */ + + P(LVL, NA), /* 02: Reserved */ + P(LVL, NA), /* 03: Reserved */ + + PLH(LVL, REM_CCE1), /* 04: FROM_L2.1_SHR ### */ + PLH(LVL, REM_CCE1), /* 05: FROM_L2.1_MOD ### */ + + PLH(LVL, REM_CCE1), /* 06: FROM_L3.1_SHR ### */ + PLH(LVL, REM_CCE1), /* 07: FROM_L3.1_MOD ### */ + + PLH(LVL, REM_CCE2), /* 08: FROM_RL2L3_SHR ### */ + PLH(LVL, REM_CCE2), /* 09: FROM_RL2L3_MOD ### */ + + PLH(LVL, REM_CCE2), /* 10: FROM_DL2L3_SHR ### */ + PLH(LVL, REM_CCE2), /* 11: FROM_DL2L3_MOD ### */ + + PLH(LVL, LOC_RAM), /* 12: FROM_LMEM */ + PLH(LVL, REM_RAM2), /* 13: FROM_RMEM ### */ + PLH(LVL, REM_RAM2), /* 14: FROM_DMEM */ + + P(LVL, NA), /* 15: Reserved */ +}; + +/* + * Determine the memory-hierarchy information (if applicable) for the + * instruction/address we are sampling. If we encountered a DCACHE_MISS, + * mmcra[DCACHE_SRC_MASK] specifies the memory level from which the operand + * was loaded. + * + * Otherwise, it is an L1-hit, provided the instruction was a load/store. + */ +static void power7_get_mem_data_src(union perf_mem_data_src *dsrc, + struct pt_regs *regs) +{ + u64 idx; + u64 mmcra = regs->dsisr; + u64 addr; + int ret; + unsigned int instr; + + if (mmcra & POWER7_MMCRA_DCACHE_MISS) { + idx = mmcra & POWER7_MMCRA_DCACHE_SRC_MASK; + idx >>= POWER7_MMCRA_DCACHE_SRC_SHIFT; + + dsrc->val |= dcache_src_map[idx]; + return; + } + + instr = 0; + addr = perf_instruction_pointer(regs); + + if (is_kernel_addr(addr)) + instr = *(unsigned int *)addr; + else { + pagefault_disable(); + ret = __get_user_inatomic(instr, (unsigned int __user *)addr); + pagefault_enable(); + if (ret) + instr = 0; + } + if (instr && instr_is_load_store(&instr)) + dsrc->val |= PLH(LVL, L1); +} + + static int power7_generic_events[] = { [PERF_COUNT_HW_CPU_CYCLES] = PME_PM_CYC, [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PME_PM_GCT_NOSLOT_CYC, @@ -437,6 +530,7 @@ static struct power_pmu power7_pmu = { .get_constraint = power7_get_constraint, .get_alternatives = power7_get_alternatives, .disable_pmc = power7_disable_pmc, + .get_mem_data_src = power7_get_mem_data_src, .flags = PPMU_ALT_SIPR, .attr_groups = power7_pmu_attr_groups, .n_generic = ARRAY_SIZE(power7_generic_events),
On Power7, the DCACHE_SRC field in MMCRA register identifies the memory hierarchy level (eg: L2, L3 etc) from which a data-cache miss for a marked instruction was satisfied. Use the 'perf_mem_data_src' object to export this hierarchy level to user space. Some memory hierarchy levels in Power7 don't map into the arch-neutral levels. However, since newer generation of the processor (i.e. Power8) uses fewer levels than in Power7, we don't really need to define new hierarchy levels just for Power7. We instead, map as many levels as possible and approximate the rest. See comments near dcache-src_map[] in the patch. Usage: perf record -d -e 'cpu/PM_MRK_GRP_CMPL/' <application> perf report -n --mem-mode --sort=mem,sym,dso,symbol_daddr,dso_daddr" For samples involving load/store instructions, the memory hierarchy level is shown as "L1 hit", "Remote RAM hit" etc. # or perf record --data <application> perf report -D Sample records contain a 'data_src' field which encodes the memory hierarchy level: Eg: data_src 0x442 indicates MEM_OP_LOAD, MEM_LVL_HIT, MEM_LVL_L2 (i.e load hit L2). Note that the PMU event PM_MRK_GRP_CMPL tracks all marked group completions events. While some of these are loads and stores, others like 'add' instructions may also be sampled. As such, the precise semantics of 'perf mem -t load' or 'perf mem -t store' (which require sampling only loads or only stores cannot be implemented on Power. (Sampling on PM_MRK_GRP_CMPL and throwing away non-loads and non-store samples could yield an inconsistent profile of the application). Thanks to input from Stephane Eranian, Michael Ellerman and Michael Neuling. Cc: Stephane Eranian <eranian@google.com> Cc: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> --- Changelog[v4]: Drop support for 'perf mem' for Power (use perf-record and perf-report directly) Changelog[v3]: [Michael Ellerman] If newer levels that we defined in [v2] are not needed for Power8, ignore the new levels for Power7 also, and approximate them. Separate the TLB level mapping to a separate patchset. Changelog[v2]: [Stephane Eranian] Define new levels rather than ORing the L2 and L3 with REM_CCE1 and REM_CCE2. [Stephane Eranian] allocate a bit PERF_MEM_XLVL_NA for architectures that don't use the ->mem_xlvl field. Insert the TLB patch ahead so the new TLB bits are contigous with existing TLB bits. arch/powerpc/perf/power7-pmu.c | 94 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+)