| Message ID | 1319652797-28017-1-git-send-email-msm@freescale.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
> @@ -1759,6 +1760,12 @@ void mpic_reset_core(int cpu) > pir &= ~(1 << cpuid); > mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); > mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); > + > + /* Perform 15 EOI on each reset core to clear pending interrupts */ > + for (i = 0; i < 15; i++) { > + _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], > + MPIC_CPU_EOI, 0); > + } This is generic code, right? Please add info to the comment about which devices need this quirk, then. Segher
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 9678081..f5b83f0 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -1748,6 +1748,7 @@ void mpic_reset_core(int cpu) struct mpic *mpic = mpic_primary; u32 pir; int cpuid = get_hard_smp_processor_id(cpu); + int i; /* Set target bit for core reset */ pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); @@ -1759,6 +1760,12 @@ void mpic_reset_core(int cpu) pir &= ~(1 << cpuid); mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); + + /* Perform 15 EOI on each reset core to clear pending interrupts */ + for (i = 0; i < 15; i++) { + _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], + MPIC_CPU_EOI, 0); + } } #endif /* CONFIG_SMP */
This is listed as a requirement for Freescale CoreNet based devices (e.g p4080ds with MPIC v4.x) after issuing a core reset to properly clear pending interrupts. Signed-off-by: Matthew McClintock <msm@freescale.com> --- v2: Updated commit message arch/powerpc/sysdev/mpic.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)