diff mbox

[09/15] powerpc: Initialize LPCR:DPFD on power7 to a sane default

Message ID 1301984051-18413-10-git-send-email-benh@kernel.crashing.org (mailing list archive)
State Accepted, archived
Commit 895796a8ab548fe03b6fea410dcb1b86e1913708
Headers show

Commit Message

Benjamin Herrenschmidt April 5, 2011, 6:14 a.m. UTC
This sets the default data stream prefetch size for operating
systems that don't set their own value in DSCR. We use 4 which
is "medium".

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 arch/powerpc/kernel/cpu_setup_power7.S |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)
diff mbox

Patch

diff --git a/arch/powerpc/kernel/cpu_setup_power7.S b/arch/powerpc/kernel/cpu_setup_power7.S
index e801ef1..2390f6f 100644
--- a/arch/powerpc/kernel/cpu_setup_power7.S
+++ b/arch/powerpc/kernel/cpu_setup_power7.S
@@ -54,6 +54,7 @@  __init_LPCR:
 	 *
 	 *   LPES = 0b01 (HSRR0/1 used for 0x500)
 	 *   PECE = 0b111
+	 *   DPFD = 4
 	 *
 	 * Other bits untouched for now
 	 */
@@ -61,6 +62,12 @@  __init_LPCR:
 	ori	r3,r3,(LPCR_LPES0|LPCR_LPES1)
 	xori	r3,r3, LPCR_LPES0
 	ori	r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
+	li	r5,7
+	sldi	r5,r5,LPCR_DPFD_SH
+	andc	r3,r3,r5
+	li	r5,4
+	sldi	r5,r5,LPCR_DPFD_SH
+	or	r3,r3,r5
 	mtspr	SPRN_LPCR,r3
 	isync
 	blr