diff mbox series

[RFC,v5,9/9] arm64: tegra: Add Tegra VI CSI support in device tree

Message ID 1584985955-19101-10-git-send-email-skomatineni@nvidia.com
State New
Headers show
Series Add Tegra driver for video capture | expand

Commit Message

Sowjanya Komatineni March 23, 2020, 5:52 p.m. UTC
Tegra210 contains VI controller for video input capture from MIPI
CSI camera sensors and also supports built-in test pattern generator.

CSI ports can be one-to-one mapped to VI channels for capturing from
an external sensor or from built-in test pattern generator.

This patch adds support for VI and CSI and enables them in Tegra210
device tree.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++
 arch/arm64/boot/dts/nvidia/tegra210.dtsi       | 45 +++++++++++++++++++++++++-
 2 files changed, 54 insertions(+), 1 deletion(-)

Comments

Dmitry Osipenko March 24, 2020, 7:19 p.m. UTC | #1
23.03.2020 20:52, Sowjanya Komatineni пишет:
...
> +			pd_venc: venc {
> +				clocks = <&tegra_car TEGRA210_CLK_VI>,
> +					 <&tegra_car TEGRA210_CLK_CSI>;
> +				resets = <&mc TEGRA210_MC_RESET_VI>,

The MC resetting should be needed only for a hardware hot-resetting. It
should be wrong to add it to the power domain.

> +					 <&tegra_car TEGRA210_RST_VI>,
> +					 <&tegra_car TEGRA210_CLK_CSI>;
> +				#power-domain-cells = <0>;
> +			};
>  		};
Sowjanya Komatineni March 24, 2020, 9:04 p.m. UTC | #2
On 3/24/20 12:19 PM, Dmitry Osipenko wrote:
> External email: Use caution opening links or attachments
>
>
> 23.03.2020 20:52, Sowjanya Komatineni пишет:
> ...
>> +                     pd_venc: venc {
>> +                             clocks = <&tegra_car TEGRA210_CLK_VI>,
>> +                                      <&tegra_car TEGRA210_CLK_CSI>;
>> +                             resets = <&mc TEGRA210_MC_RESET_VI>,
> The MC resetting should be needed only for a hardware hot-resetting. It
> should be wrong to add it to the power domain.
TRM recommends to do MC client hot-reset during VE power gate and ungate.
>
>> +                                      <&tegra_car TEGRA210_RST_VI>,
>> +                                      <&tegra_car TEGRA210_CLK_CSI>;
>> +                             #power-domain-cells = <0>;
>> +                     };
>>                };
Dmitry Osipenko March 24, 2020, 10:48 p.m. UTC | #3
25.03.2020 00:04, Sowjanya Komatineni пишет:
> 
> On 3/24/20 12:19 PM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> 23.03.2020 20:52, Sowjanya Komatineni пишет:
>> ...
>>> +                     pd_venc: venc {
>>> +                             clocks = <&tegra_car TEGRA210_CLK_VI>,
>>> +                                      <&tegra_car TEGRA210_CLK_CSI>;
>>> +                             resets = <&mc TEGRA210_MC_RESET_VI>,
>> The MC resetting should be needed only for a hardware hot-resetting. It
>> should be wrong to add it to the power domain.
> TRM recommends to do MC client hot-reset during VE power gate and ungate.

Could you please tell what TRM it is and what's the page#?
Sowjanya Komatineni March 25, 2020, 12:01 a.m. UTC | #4
On 3/24/20 3:48 PM, Dmitry Osipenko wrote:
> External email: Use caution opening links or attachments
>
>
> 25.03.2020 00:04, Sowjanya Komatineni пишет:
>> On 3/24/20 12:19 PM, Dmitry Osipenko wrote:
>>> External email: Use caution opening links or attachments
>>>
>>>
>>> 23.03.2020 20:52, Sowjanya Komatineni пишет:
>>> ...
>>>> +                     pd_venc: venc {
>>>> +                             clocks = <&tegra_car TEGRA210_CLK_VI>,
>>>> +                                      <&tegra_car TEGRA210_CLK_CSI>;
>>>> +                             resets = <&mc TEGRA210_MC_RESET_VI>,
>>> The MC resetting should be needed only for a hardware hot-resetting. It
>>> should be wrong to add it to the power domain.
>> TRM recommends to do MC client hot-reset during VE power gate and ungate.
> Could you please tell what TRM it is and what's the page#?
Tegra TX1 TRM Page 425, Section 12.2.7.14 Procedures for VE Power Domains
Dmitry Osipenko March 25, 2020, 12:22 a.m. UTC | #5
25.03.2020 03:01, Sowjanya Komatineni пишет:
> 
> On 3/24/20 3:48 PM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> 25.03.2020 00:04, Sowjanya Komatineni пишет:
>>> On 3/24/20 12:19 PM, Dmitry Osipenko wrote:
>>>> External email: Use caution opening links or attachments
>>>>
>>>>
>>>> 23.03.2020 20:52, Sowjanya Komatineni пишет:
>>>> ...
>>>>> +                     pd_venc: venc {
>>>>> +                             clocks = <&tegra_car TEGRA210_CLK_VI>,
>>>>> +                                      <&tegra_car TEGRA210_CLK_CSI>;
>>>>> +                             resets = <&mc TEGRA210_MC_RESET_VI>,
>>>> The MC resetting should be needed only for a hardware hot-resetting. It
>>>> should be wrong to add it to the power domain.
>>> TRM recommends to do MC client hot-reset during VE power gate and
>>> ungate.
>> Could you please tell what TRM it is and what's the page#?
> Tegra TX1 TRM Page 425, Section 12.2.7.14 Procedures for VE Power Domains

Okay, thanks.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index 313a4c2..b57d837 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -14,6 +14,16 @@ 
 			status = "okay";
 		};
 
+		vi@54080000 {
+			status = "okay";
+
+			avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+
+			csi@838 {
+				status = "okay";
+			};
+		};
+
 		sor@54580000 {
 			status = "okay";
 
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 5b1dfd8..2deba87 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -137,9 +137,43 @@ 
 
 		vi@54080000 {
 			compatible = "nvidia,tegra210-vi";
-			reg = <0x0 0x54080000 0x0 0x00040000>;
+			reg = <0x0 0x54080000 0x0 0x700>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
+			assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
+			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+
+			clocks = <&tegra_car TEGRA210_CLK_VI>;
+			clock-names = "vi";
+			power-domains = <&pd_venc>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0x0 0x0 0x54080000 0x2000>;
+
+			csi@838 {
+				compatible = "nvidia,tegra210-csi";
+				reg = <0x838 0x1300>;
+				status = "disabled";
+				assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
+						  <&tegra_car TEGRA210_CLK_CILCD>,
+						  <&tegra_car TEGRA210_CLK_CILE>;
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
+							 <&tegra_car TEGRA210_CLK_PLL_P>,
+							 <&tegra_car TEGRA210_CLK_PLL_P>;
+				assigned-clock-rates = <102000000>,
+						       <102000000>,
+						       <102000000>;
+
+				clocks = <&tegra_car TEGRA210_CLK_CSI>,
+					 <&tegra_car TEGRA210_CLK_CILAB>,
+					 <&tegra_car TEGRA210_CLK_CILCD>,
+					 <&tegra_car TEGRA210_CLK_CILE>;
+				clock-names = "csi", "cilab", "cilcd", "cile";
+				power-domains = <&pd_sor>;
+			};
+
 		};
 
 		tsec@54100000 {
@@ -839,6 +873,15 @@ 
 				reset-names = "vic";
 				#power-domain-cells = <0>;
 			};
+
+			pd_venc: venc {
+				clocks = <&tegra_car TEGRA210_CLK_VI>,
+					 <&tegra_car TEGRA210_CLK_CSI>;
+				resets = <&mc TEGRA210_MC_RESET_VI>,
+					 <&tegra_car TEGRA210_RST_VI>,
+					 <&tegra_car TEGRA210_CLK_CSI>;
+				#power-domain-cells = <0>;
+			};
 		};
 
 		sdmmc1_3v3: sdmmc1-3v3 {