| Message ID | 1584985955-19101-3-git-send-email-skomatineni@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show
Return-Path: <linux-tegra-owner@vger.kernel.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=D+lp2bsH; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48mMS00j8Zz9sSH for <incoming@patchwork.ozlabs.org>; Tue, 24 Mar 2020 04:53:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727558AbgCWRwk (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); Mon, 23 Mar 2020 13:52:40 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:15183 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726991AbgCWRwj (ORCPT <rfc822;linux-tegra@vger.kernel.org>); Mon, 23 Mar 2020 13:52:39 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id <B5e78f7590000>; Mon, 23 Mar 2020 10:52:25 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 10:52:38 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 23 Mar 2020 10:52:38 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 17:52:37 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 23 Mar 2020 17:52:38 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.78]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id <B5e78f7650000>; Mon, 23 Mar 2020 10:52:37 -0700 From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <skomatineni@nvidia.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>, <helen.koike@collabora.com> CC: <digetx@gmail.com>, <sboyd@kernel.org>, <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [RFC PATCH v5 2/9] arm64: tegra: Add reset-cells to mc Date: Mon, 23 Mar 2020 10:52:28 -0700 Message-ID: <1584985955-19101-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584985945; bh=fypsljnYXUQBk09pkBuzFp0S2nxT0B9eauugx/SlCBI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=D+lp2bsHUM0j1Mooa5iWCSWjI+AJKFKJDy/CcMi9+rIVh6sOTQBtWiTsjdc1pgEK8 Zmu7vUJqY2JUndCkSmyO0/tufGtzTt9A7p4B27bhfnWGkDJkon+KCDYw8t0IxF/mmd NY8CZX+G+a6+zO30g8MlPqx27lpP19KVowgWMvVT0woigrnv6Zie3bbtMoFSI168J4 adbQfaUBDLrBioOVqHV3J2GWxRtbPoX8v2QpMKFFZhnN07dRszzYm94SGQXiYa45BB 9zePh7f7xvgBAQHU8mJYYv8ag2gBSYKAgx0v9Ka9cgSRp1CiII1dWfkimeXQq9FToK DDE0Dw2/JPZ3g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: <linux-tegra.vger.kernel.org> X-Mailing-List: linux-tegra@vger.kernel.org |
| Series |
Add Tegra driver for video capture
|
expand
|
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index d0eff92..5b1dfd8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -894,6 +894,7 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; + #reset-cells = <1>; }; sata@70020000 {
Tegra210 device tree is missing reset-cells property for mc node. This patch fixes it. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+)