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[17/29] mmp: correct nand clock setting for pxa168 and pxa910

Message ID AANLkTin4vm2oxiRv=Zuoujdk9G8ojmsDgmiJKNWkv1Cg@mail.gmail.com
State New, archived
Headers show

Commit Message

Haojian Zhuang July 28, 2010, 5:57 a.m. UTC 
From 6fcc38f6e3429ed972b2a45856d70b8e69db8f35 Mon Sep 17 00:00:00 2001
From: Lei Wen <leiwen@marvell.com>
Date: Thu, 3 Jun 2010 15:46:50 +0800
Subject: [PATCH 17/29] mmp: correct nand clock setting for pxa168 and pxa910

There is no clock setting at 208Mhz for nand on pxa168 and pxa910
platform. Set correct register and lock the clock at
156MHZ.

Signed-off-by: Lei Wen <leiwen@marvell.com>
---
 arch/arm/mach-mmp/pxa168.c |    2 +-
 arch/arm/mach-mmp/pxa910.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 652ae66..70d2231 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -78,7 +78,7 @@  static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
 static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);

-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19B, 156000000);

 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 46f2d69..96f2b61 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,7 +110,7 @@  static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);

-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19B, 156000000);

 /* device and clock bindings */
 static struct clk_lookup pxa910_clkregs[] = {