From patchwork Wed Jul 28 05:57:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 60101 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5C40A1007D1 for ; Wed, 28 Jul 2010 16:05:28 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1Odzio-0008Go-Hy; Wed, 28 Jul 2010 06:02:33 +0000 Received: from mail-px0-f177.google.com ([209.85.212.177]) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OdzeD-0002n7-58; Wed, 28 Jul 2010 05:57:46 +0000 Received: by mail-px0-f177.google.com with SMTP id 13so924820pxi.36 for ; Tue, 27 Jul 2010 22:57:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=WzUbCZpdUlZAgpLDifdbupmBkczxsH017wqjk2VpXgU=; b=sCJRrBD7RNhadu2SsVMXHq44Lcjjdtvk0F72XmBI3FpHTkvJYwATFvDL7rO4wB82n0 xnH6NGdZPAzSXrfCyCXVKWZiS8KNfeaCAiZ3otsdaNjQNBWvcZ0uMZNESsONZhJ8thVz C8Jr3O3dEoPyt66WIzgcPCp0JoGzcPP3DFMBw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=F4SaXGXs0Tae7E8NN9IvjQ1LiI23vtVLZAYnZUAdttpu/lBJPBwks+WxOXj1hEc47s MqkwAKTdyITCLgdGUaMW8DztCRf52T3cGlZkzAlv66ErejzTj5n2Ar8Xxk+8gXmGWato behf996xy08l628G7pDHZ6xRhzrY7uuFgcBkE= MIME-Version: 1.0 Received: by 10.142.166.6 with SMTP id o6mr11479612wfe.237.1280296664736; Tue, 27 Jul 2010 22:57:44 -0700 (PDT) Received: by 10.142.54.6 with HTTP; Tue, 27 Jul 2010 22:57:44 -0700 (PDT) Date: Wed, 28 Jul 2010 13:57:44 +0800 Message-ID: Subject: [PATCH 17/29] mmp: correct nand clock setting for pxa168 and pxa910 From: Haojian Zhuang To: Eric Miao , linux-arm-kernel , David Woodhouse , David Woodhouse , Marc Kleine-Budde , linux-mtd@lists.infradead.org, Lei Wen X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100728_015746_065720_6AE6A950 X-CRM114-Status: GOOD ( 14.24 ) X-Spam-Score: -0.1 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is freemail (haojian.zhuang[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From 6fcc38f6e3429ed972b2a45856d70b8e69db8f35 Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Thu, 3 Jun 2010 15:46:50 +0800 Subject: [PATCH 17/29] mmp: correct nand clock setting for pxa168 and pxa910 There is no clock setting at 208Mhz for nand on pxa168 and pxa910 platform. Set correct register and lock the clock at 156MHZ. Signed-off-by: Lei Wen --- arch/arm/mach-mmp/pxa168.c | 2 +- arch/arm/mach-mmp/pxa910.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 652ae66..70d2231 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -78,7 +78,7 @@ static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); -static APMU_CLK(nand, NAND, 0x01db, 208000000); +static APMU_CLK(nand, NAND, 0x19B, 156000000); /* device and clock bindings */ static struct clk_lookup pxa168_clkregs[] = { diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 46f2d69..96f2b61 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -110,7 +110,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); -static APMU_CLK(nand, NAND, 0x01db, 208000000); +static APMU_CLK(nand, NAND, 0x19B, 156000000); /* device and clock bindings */ static struct clk_lookup pxa910_clkregs[] = {