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i2c: rcar: enable interrupts before starting transfer

Message ID 20210915134827.13043-1-wsa+renesas@sang-engineering.com
State Accepted
Headers show
Series i2c: rcar: enable interrupts before starting transfer | expand

Commit Message

Wolfram Sang Sept. 15, 2021, 1:48 p.m. UTC
We want to enable the interrupts _before_ starting the transfer because
it is good programming style and also the proposed order in the R-Car
manual. There is no difference in practice because it doesn't matter in
which order both conditions appear if we wait for both to happen.

Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/i2c/busses/i2c-rcar.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Niklas Söderlund Sept. 20, 2021, 5:43 p.m. UTC | #1
Hi Wolfram,

Thanks for your patch.

On 2021-09-15 15:48:27 +0200, Wolfram Sang wrote:
> We want to enable the interrupts _before_ starting the transfer because
> it is good programming style and also the proposed order in the R-Car
> manual. There is no difference in practice because it doesn't matter in
> which order both conditions appear if we wait for both to happen.
> 
> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> ---
>  drivers/i2c/busses/i2c-rcar.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> index bff9913c37b8..fc13511f4562 100644
> --- a/drivers/i2c/busses/i2c-rcar.c
> +++ b/drivers/i2c/busses/i2c-rcar.c
> @@ -339,6 +339,9 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
>  		priv->flags |= ID_LAST_MSG;
>  
>  	rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
> +	if (!priv->atomic_xfer)
> +		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
> +
>  	/*
>  	 * We don't have a test case but the HW engineers say that the write order
>  	 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
> @@ -354,9 +357,6 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
>  			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
>  		rcar_i2c_write(priv, ICMSR, 0);
>  	}
> -
> -	if (!priv->atomic_xfer)
> -		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
>  }
>  
>  static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
> -- 
> 2.30.2
>
Ulrich Hecht Sept. 21, 2021, 10:46 a.m. UTC | #2
> On 09/15/2021 3:48 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote:
> 
>  
> We want to enable the interrupts _before_ starting the transfer because
> it is good programming style and also the proposed order in the R-Car
> manual. There is no difference in practice because it doesn't matter in
> which order both conditions appear if we wait for both to happen.
> 
> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  drivers/i2c/busses/i2c-rcar.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> index bff9913c37b8..fc13511f4562 100644
> --- a/drivers/i2c/busses/i2c-rcar.c
> +++ b/drivers/i2c/busses/i2c-rcar.c
> @@ -339,6 +339,9 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
>  		priv->flags |= ID_LAST_MSG;
>  
>  	rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
> +	if (!priv->atomic_xfer)
> +		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
> +
>  	/*
>  	 * We don't have a test case but the HW engineers say that the write order
>  	 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
> @@ -354,9 +357,6 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
>  			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
>  		rcar_i2c_write(priv, ICMSR, 0);
>  	}
> -
> -	if (!priv->atomic_xfer)
> -		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
>  }
>  
>  static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
> -- 
> 2.30.2

Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>

CU
Uli
Wolfram Sang Sept. 29, 2021, 9:03 p.m. UTC | #3
On Wed, Sep 15, 2021 at 03:48:27PM +0200, Wolfram Sang wrote:
> We want to enable the interrupts _before_ starting the transfer because
> it is good programming style and also the proposed order in the R-Car
> manual. There is no difference in practice because it doesn't matter in
> which order both conditions appear if we wait for both to happen.
> 
> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Applied to for-next, thanks!
diff mbox series

Patch

diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index bff9913c37b8..fc13511f4562 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -339,6 +339,9 @@  static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
 		priv->flags |= ID_LAST_MSG;
 
 	rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
+	if (!priv->atomic_xfer)
+		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
+
 	/*
 	 * We don't have a test case but the HW engineers say that the write order
 	 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
@@ -354,9 +357,6 @@  static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
 			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
 		rcar_i2c_write(priv, ICMSR, 0);
 	}
-
-	if (!priv->atomic_xfer)
-		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
 }
 
 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)