| Message ID | 20201104152455.40627-3-quarium@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | gpio: pcie-idio-24: Fix IRQ handling | expand |
On Wed, Nov 04, 2020 at 04:24:54PM +0100, Arnaud de Turckheim wrote: > This fixes the COS Enable Register value for enabling/disabling the > corresponding IRQs bank. > > Fixes: 585562046628 ("gpio: Add GPIO support for the ACCES PCIe-IDIO-24 family") > Signed-off-by: Arnaud de Turckheim <quarium@gmail.com> Reviewed-by: William Breathitt Gray <vilhelm.gray@gmail.com> > --- > drivers/gpio/gpio-pcie-idio-24.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpio/gpio-pcie-idio-24.c b/drivers/gpio/gpio-pcie-idio-24.c > index 5ea517416366..a61de14d09b6 100644 > --- a/drivers/gpio/gpio-pcie-idio-24.c > +++ b/drivers/gpio/gpio-pcie-idio-24.c > @@ -334,13 +334,13 @@ static void idio_24_irq_mask(struct irq_data *data) > unsigned long flags; > const unsigned long bit_offset = irqd_to_hwirq(data) - 24; > unsigned char new_irq_mask; > - const unsigned long bank_offset = bit_offset/8 * 8; > + const unsigned long bank_offset = bit_offset / 8; > unsigned char cos_enable_state; > > raw_spin_lock_irqsave(&idio24gpio->lock, flags); > > idio24gpio->irq_mask &= ~BIT(bit_offset); > - new_irq_mask = idio24gpio->irq_mask >> bank_offset; > + new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; > > if (!new_irq_mask) { > cos_enable_state = ioread8(&idio24gpio->reg->cos_enable); > @@ -363,12 +363,12 @@ static void idio_24_irq_unmask(struct irq_data *data) > unsigned long flags; > unsigned char prev_irq_mask; > const unsigned long bit_offset = irqd_to_hwirq(data) - 24; > - const unsigned long bank_offset = bit_offset/8 * 8; > + const unsigned long bank_offset = bit_offset / 8; > unsigned char cos_enable_state; > > raw_spin_lock_irqsave(&idio24gpio->lock, flags); > > - prev_irq_mask = idio24gpio->irq_mask >> bank_offset; > + prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; > idio24gpio->irq_mask |= BIT(bit_offset); > > if (!prev_irq_mask) { > -- > 2.25.1 >
diff --git a/drivers/gpio/gpio-pcie-idio-24.c b/drivers/gpio/gpio-pcie-idio-24.c index 5ea517416366..a61de14d09b6 100644 --- a/drivers/gpio/gpio-pcie-idio-24.c +++ b/drivers/gpio/gpio-pcie-idio-24.c @@ -334,13 +334,13 @@ static void idio_24_irq_mask(struct irq_data *data) unsigned long flags; const unsigned long bit_offset = irqd_to_hwirq(data) - 24; unsigned char new_irq_mask; - const unsigned long bank_offset = bit_offset/8 * 8; + const unsigned long bank_offset = bit_offset / 8; unsigned char cos_enable_state; raw_spin_lock_irqsave(&idio24gpio->lock, flags); idio24gpio->irq_mask &= ~BIT(bit_offset); - new_irq_mask = idio24gpio->irq_mask >> bank_offset; + new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; if (!new_irq_mask) { cos_enable_state = ioread8(&idio24gpio->reg->cos_enable); @@ -363,12 +363,12 @@ static void idio_24_irq_unmask(struct irq_data *data) unsigned long flags; unsigned char prev_irq_mask; const unsigned long bit_offset = irqd_to_hwirq(data) - 24; - const unsigned long bank_offset = bit_offset/8 * 8; + const unsigned long bank_offset = bit_offset / 8; unsigned char cos_enable_state; raw_spin_lock_irqsave(&idio24gpio->lock, flags); - prev_irq_mask = idio24gpio->irq_mask >> bank_offset; + prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; idio24gpio->irq_mask |= BIT(bit_offset); if (!prev_irq_mask) {
This fixes the COS Enable Register value for enabling/disabling the corresponding IRQs bank. Fixes: 585562046628 ("gpio: Add GPIO support for the ACCES PCIe-IDIO-24 family") Signed-off-by: Arnaud de Turckheim <quarium@gmail.com> --- drivers/gpio/gpio-pcie-idio-24.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)