diff mbox series

[RFC,2/3] RISC-V: hwprobe: Add Zawrs test bit

Message ID 20240418094635.3502009-3-christoph.muellner@vrull.eu
State New
Headers show
Series RISC-V: Use WRS.STO for atomic_spin_nop | expand

Commit Message

Christoph Müllner April 18, 2024, 9:46 a.m. UTC 
This patch adds a hwprobe test bit for Zawrs.
The bit position is not settled as the corresponding kernel
patch did not land upstream so far:
  https://lore.kernel.org/all/20240315134009.580167-10-ajones@ventanamicro.com/

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
index 4856189f3c..16526c3aec 100644
--- a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
+++ b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
@@ -79,6 +79,7 @@  struct riscv_hwprobe {
 #define  RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
 #define  RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
 #define  RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
+#define  RISCV_HWPROBE_EXT_ZAWRS (1ULL << 36)
 #define RISCV_HWPROBE_KEY_CPUPERF_0 5
 #define  RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
 #define  RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)