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[95.217.130.239]) by smtp.gmail.com with ESMTPSA id b14-20020a056512060e00b00516d217f688sm169759lfe.295.2024.04.18.02.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 02:46:41 -0700 (PDT) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: libc-alpha@sourceware.org, Adhemerval Zanella , Palmer Dabbelt , Darius Rad , Andrew Waterman , Philipp Tomsich , Evan Green , Kito Cheng , Jeff Law , Vineet Gupta Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [RFC PATCH 1/3] RISC-V: Sync hwprobe: Sync extension bits with Linux 6.8 Date: Thu, 18 Apr 2024 11:46:33 +0200 Message-ID: <20240418094635.3502009-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240418094635.3502009-1-christoph.muellner@vrull.eu> References: <20240418094635.3502009-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org This patch imports additional extension bits for hwprobe from Linux 6.8. This patch does not change existing behaviour as non of the newly defined bits are used anywhere. Signed-off-by: Christoph Müllner --- sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h | 29 +++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h index 8ecb43bb69..4856189f3c 100644 --- a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h +++ b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h @@ -50,6 +50,35 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) #define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) +#define RISCV_HWPROBE_EXT_ZBC (1 << 7) +#define RISCV_HWPROBE_EXT_ZBKB (1 << 8) +#define RISCV_HWPROBE_EXT_ZBKC (1 << 9) +#define RISCV_HWPROBE_EXT_ZBKX (1 << 10) +#define RISCV_HWPROBE_EXT_ZKND (1 << 11) +#define RISCV_HWPROBE_EXT_ZKNE (1 << 12) +#define RISCV_HWPROBE_EXT_ZKNH (1 << 13) +#define RISCV_HWPROBE_EXT_ZKSED (1 << 14) +#define RISCV_HWPROBE_EXT_ZKSH (1 << 15) +#define RISCV_HWPROBE_EXT_ZKT (1 << 16) +#define RISCV_HWPROBE_EXT_ZVBB (1 << 17) +#define RISCV_HWPROBE_EXT_ZVBC (1 << 18) +#define RISCV_HWPROBE_EXT_ZVKB (1 << 19) +#define RISCV_HWPROBE_EXT_ZVKG (1 << 20) +#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21) +#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22) +#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23) +#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24) +#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25) +#define RISCV_HWPROBE_EXT_ZVKT (1 << 26) +#define RISCV_HWPROBE_EXT_ZFH (1 << 27) +#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28) +#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29) +#define RISCV_HWPROBE_EXT_ZVFH (1 << 30) +#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) +#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) +#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) +#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) +#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) From patchwork Thu Apr 18 09:46:34 2024 Content-Type: text/plain; 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[95.217.130.239]) by smtp.gmail.com with ESMTPSA id b14-20020a056512060e00b00516d217f688sm169759lfe.295.2024.04.18.02.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 02:46:43 -0700 (PDT) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: libc-alpha@sourceware.org, Adhemerval Zanella , Palmer Dabbelt , Darius Rad , Andrew Waterman , Philipp Tomsich , Evan Green , Kito Cheng , Jeff Law , Vineet Gupta Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [RFC PATCH 2/3] RISC-V: hwprobe: Add Zawrs test bit Date: Thu, 18 Apr 2024 11:46:34 +0200 Message-ID: <20240418094635.3502009-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240418094635.3502009-1-christoph.muellner@vrull.eu> References: <20240418094635.3502009-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org This patch adds a hwprobe test bit for Zawrs. The bit position is not settled as the corresponding kernel patch did not land upstream so far: https://lore.kernel.org/all/20240315134009.580167-10-ajones@ventanamicro.com/ Signed-off-by: Christoph Müllner --- sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h | 1 + 1 file changed, 1 insertion(+) diff --git a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h index 4856189f3c..16526c3aec 100644 --- a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h +++ b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h @@ -79,6 +79,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) +#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 36) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) From patchwork Thu Apr 18 09:46:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1924882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[95.217.130.239]) by smtp.gmail.com with ESMTPSA id b14-20020a056512060e00b00516d217f688sm169759lfe.295.2024.04.18.02.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 02:46:44 -0700 (PDT) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: libc-alpha@sourceware.org, Adhemerval Zanella , Palmer Dabbelt , Darius Rad , Andrew Waterman , Philipp Tomsich , Evan Green , Kito Cheng , Jeff Law , Vineet Gupta Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [RFC PATCH 3/3] RISC-V: Implement CPU yielding for busy loops with Zihintpause/Zawrs Date: Thu, 18 Apr 2024 11:46:35 +0200 Message-ID: <20240418094635.3502009-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240418094635.3502009-1-christoph.muellner@vrull.eu> References: <20240418094635.3502009-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org The macro atomic_spin_nop can be used to implement arch-specific CPU yielding that is used in busy loops (e.g. in pthread_spin_lock). This patch introduces an ifunc-based implementation for RISC-V, that uses Zihintpause's PAUSE instruction for that matter (as PAUSE is a HINT instruction there is not dependency to Zihintpause at runtime). Further, we test for Zawrs via hwprobe() and if found we use WRS.STO instead of PAUSE. Signed-off-by: Christoph Müllner --- sysdeps/riscv/multiarch/cpu-relax_generic.S | 31 +++++++++++++++ sysdeps/riscv/multiarch/cpu-relax_zawrs.S | 28 +++++++++++++ .../unix/sysv/linux/riscv/atomic-machine.h | 3 ++ .../unix/sysv/linux/riscv/multiarch/Makefile | 8 ++++ .../sysv/linux/riscv/multiarch/cpu-relax.c | 39 +++++++++++++++++++ .../linux/riscv/multiarch/ifunc-impl-list.c | 32 +++++++++++++-- 6 files changed, 137 insertions(+), 4 deletions(-) create mode 100644 sysdeps/riscv/multiarch/cpu-relax_generic.S create mode 100644 sysdeps/riscv/multiarch/cpu-relax_zawrs.S create mode 100644 sysdeps/unix/sysv/linux/riscv/multiarch/cpu-relax.c diff --git a/sysdeps/riscv/multiarch/cpu-relax_generic.S b/sysdeps/riscv/multiarch/cpu-relax_generic.S new file mode 100644 index 0000000000..d3ccfdce84 --- /dev/null +++ b/sysdeps/riscv/multiarch/cpu-relax_generic.S @@ -0,0 +1,31 @@ +/* CPU strand yielding for busy loops. RISC-V version. + Copyright (C) 2024 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +#include +#include + +.option push +.option arch, +zihintpause +ENTRY (__cpu_relax_generic) + /* While we can use the `pause` instruction without + the need of Zihintpause (because it is a HINT instruction), + we still have to enable Zihintpause for the assembler. */ + pause + ret +END (__cpu_relax_generic) +.option pop diff --git a/sysdeps/riscv/multiarch/cpu-relax_zawrs.S b/sysdeps/riscv/multiarch/cpu-relax_zawrs.S new file mode 100644 index 0000000000..6d27b354df --- /dev/null +++ b/sysdeps/riscv/multiarch/cpu-relax_zawrs.S @@ -0,0 +1,28 @@ +/* CPU strand yielding for busy loops. RISC-V version with Zawrs. + Copyright (C) 2024 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +#include +#include + +.option push +.option arch, +zawrs +ENTRY (__cpu_relax_zawrs) + wrs.sto + ret +END (__cpu_relax_zawrs) +.option pop diff --git a/sysdeps/unix/sysv/linux/riscv/atomic-machine.h b/sysdeps/unix/sysv/linux/riscv/atomic-machine.h index c1c9d949a0..02b9b7a421 100644 --- a/sysdeps/unix/sysv/linux/riscv/atomic-machine.h +++ b/sysdeps/unix/sysv/linux/riscv/atomic-machine.h @@ -178,4 +178,7 @@ # error "ISAs that do not subsume the A extension are not supported" #endif /* !__riscv_atomic */ +extern void __cpu_relax (void); +#define atomic_spin_nop() __cpu_relax() + #endif /* bits/atomic.h */ diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile b/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile index fcef5659d4..0cdf37a38b 100644 --- a/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile @@ -1,3 +1,11 @@ +# nscd uses atomic_spin_nop which in turn requires cpu_relax +ifeq ($(subdir),nscd) +sysdep_routines += \ + cpu-relax \ + cpu-relax_generic \ + cpu-relax_zawrs +endif + ifeq ($(subdir),string) sysdep_routines += \ memcpy \ diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/cpu-relax.c b/sysdeps/unix/sysv/linux/riscv/multiarch/cpu-relax.c new file mode 100644 index 0000000000..5aeb120e21 --- /dev/null +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/cpu-relax.c @@ -0,0 +1,39 @@ +/* Multiple versions of cpu-relax. + All versions must be listed in ifunc-impl-list.c. + Copyright (C) 2024 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +# include +# include +# include + +void __cpu_relax (void); +extern __typeof (__cpu_relax) __cpu_relax_generic attribute_hidden; +extern __typeof (__cpu_relax) __cpu_relax_zawrs attribute_hidden; + +static inline __typeof (__cpu_relax) * +select_cpu_relax_ifunc (uint64_t dl_hwcap, __riscv_hwprobe_t hwprobe_func) +{ + unsigned long long int v; + if (__riscv_hwprobe_one (hwprobe_func, RISCV_HWPROBE_KEY_IMA_EXT_0, &v) == 0 + && (v & RISCV_HWPROBE_EXT_ZAWRS)) + return __cpu_relax_zawrs; + + return __cpu_relax_generic; +} + +riscv_libc_ifunc (__cpu_relax, select_cpu_relax_ifunc); diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c b/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c index 9f806d7a9e..9c7a8c2e1f 100644 --- a/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c @@ -20,24 +20,48 @@ #include #include +#define ARRAY_SIZE(A) (sizeof (A) / sizeof ((A)[0])) + +void __cpu_relax (void); + size_t __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, size_t max) { size_t i = max; + struct riscv_hwprobe pairs[] = { + { .key = RISCV_HWPROBE_KEY_IMA_EXT_0 }, + { .key = RISCV_HWPROBE_KEY_CPUPERF_0 }, + }; bool fast_unaligned = false; + bool has_zawrs = false; + + if (__riscv_hwprobe (pairs, ARRAY_SIZE (pairs), 0, NULL, 0) == 0) + { + struct riscv_hwprobe *pair; - struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_CPUPERF_0 }; - if (__riscv_hwprobe (&pair, 1, 0, NULL, 0) == 0 - && (pair.value & RISCV_HWPROBE_MISALIGNED_MASK) + /* RISCV_HWPROBE_KEY_IMA_EXT_0 */ + pair = &pairs[0]; + if (pair->value & RISCV_HWPROBE_EXT_ZAWRS) + has_zawrs = true; + + /* RISCV_HWPROBE_KEY_CPUPERF_0 */ + pair = &pairs[1]; + if ((pair->value & RISCV_HWPROBE_MISALIGNED_MASK) == RISCV_HWPROBE_MISALIGNED_FAST) - fast_unaligned = true; + fast_unaligned = true; + } IFUNC_IMPL (i, name, memcpy, IFUNC_IMPL_ADD (array, i, memcpy, fast_unaligned, __memcpy_noalignment) IFUNC_IMPL_ADD (array, i, memcpy, 1, __memcpy_generic)) + IFUNC_IMPL (i, name, __cpu_relax, + IFUNC_IMPL_ADD (array, i, __cpu_relax, has_zawrs, + __cpu_relax_zawrs) + IFUNC_IMPL_ADD (array, i, __cpu_relax, 1, __cpu_relax_generic)) + return 0; }