===================================================================
@@ -1241,7 +1241,6 @@ OBJS = \
auto-profile.o \
bb-reorder.o \
bitmap.o \
- bt-load.o \
builtins.o \
caller-save.o \
calls.o \
===================================================================
@@ -406,8 +406,7 @@ Objective-C and Objective-C++ Dialects}.
-falign-loops[=@var{n}[:@var{m}:[@var{n2}[:@var{m2}]]]] @gol
-fassociative-math -fauto-profile -fauto-profile[=@var{path}] @gol
-fauto-inc-dec -fbranch-probabilities @gol
--fbranch-target-load-optimize -fbranch-target-load-optimize2 @gol
--fbtr-bb-exclusive -fcaller-saves @gol
+-fcaller-saves @gol
-fcombine-stack-adjustments -fconserve-stack @gol
-fcompare-elim -fcprop-registers -fcrossjumping @gol
-fcse-follow-jumps -fcse-skip-blocks -fcx-fortran-rules @gol
@@ -11025,24 +11024,6 @@ locations inside a translation unit sinc
link time. An example of such an optimization is relaxing calls to short call
instructions.
-@item -fbranch-target-load-optimize
-@opindex fbranch-target-load-optimize
-Perform branch target register load optimization before prologue / epilogue
-threading.
-The use of target registers can typically be exposed only during reload,
-thus hoisting loads out of loops and doing inter-block scheduling needs
-a separate optimization pass.
-
-@item -fbranch-target-load-optimize2
-@opindex fbranch-target-load-optimize2
-Perform branch target register load optimization after prologue / epilogue
-threading.
-
-@item -fbtr-bb-exclusive
-@opindex fbtr-bb-exclusive
-When performing branch target register load optimization, don't reuse
-branch target registers within any basic block.
-
@item -fstdarg-opt
@opindex fstdarg-opt
Optimize the prologue of variadic argument functions with respect to usage of
===================================================================
@@ -1076,16 +1076,16 @@ Common Report Var(flag_branch_probabilit
Use profiling information for branch probabilities.
fbranch-target-load-optimize
-Common Report Var(flag_branch_target_load_optimize) Optimization
-Perform branch target load optimization before prologue / epilogue threading.
+Common Ignore
+Does nothing. Preserved for backward compatibility.
fbranch-target-load-optimize2
-Common Report Var(flag_branch_target_load_optimize2) Optimization
-Perform branch target load optimization after prologue / epilogue threading.
+Common Ignore
+Does nothing. Preserved for backward compatibility.
fbtr-bb-exclusive
-Common Report Var(flag_btr_bb_exclusive) Optimization
-Restrict target load migration not to re-use registers in any basic block.
+Common Ignore
+Does nothing. Preserved for backward compatibility.
fcall-saved-
Common Joined RejectNegative Var(common_deferred_options) Defer
===================================================================
@@ -2597,38 +2597,6 @@ DEFHOOK
bool, (const rtx_insn *follower, const rtx_insn *followee),
hook_bool_const_rtx_insn_const_rtx_insn_true)
-/* Return a register class for which branch target register
- optimizations should be applied. */
-DEFHOOK
-(branch_target_register_class,
- "This target hook returns a register class for which branch target register\n\
-optimizations should be applied. All registers in this class should be\n\
-usable interchangeably. After reload, registers in this class will be\n\
-re-allocated and loads will be hoisted out of loops and be subjected\n\
-to inter-block scheduling.",
- reg_class_t, (void),
- default_branch_target_register_class)
-
-/* Return true if branch target register optimizations should include
- callee-saved registers that are not already live during the current
- function. AFTER_PE_GEN is true if prologues and epilogues have
- already been generated. */
-DEFHOOK
-(branch_target_register_callee_saved,
- "Branch target register optimization will by default exclude callee-saved\n\
-registers\n\
-that are not already live during the current function; if this target hook\n\
-returns true, they will be included. The target code must than make sure\n\
-that all target registers in the class returned by\n\
-@samp{TARGET_BRANCH_TARGET_REGISTER_CLASS} that might need saving are\n\
-saved. @var{after_prologue_epilogue_gen} indicates if prologues and\n\
-epilogues have already been generated. Note, even if you only return\n\
-true when @var{after_prologue_epilogue_gen} is false, you still are likely\n\
-to have to make special provisions in @code{INITIAL_ELIMINATION_OFFSET}\n\
-to reserve space for caller-saved target registers.",
- bool, (bool after_prologue_epilogue_gen),
- hook_bool_bool_false)
-
/* Return true if the target supports conditional execution. */
DEFHOOK
(have_conditional_execution,
===================================================================
@@ -8001,10 +8001,6 @@ build_type_attribute_variant (@var{mdecl
@hook TARGET_CANNOT_MODIFY_JUMPS_P
-@hook TARGET_BRANCH_TARGET_REGISTER_CLASS
-
-@hook TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
-
@hook TARGET_HAVE_CONDITIONAL_EXECUTION
@hook TARGET_GEN_CCMP_FIRST
===================================================================
@@ -11755,28 +11755,6 @@ cannot_modify_jumps_past_reload_p ()
@end smallexample
@end deftypefn
-@deftypefn {Target Hook} reg_class_t TARGET_BRANCH_TARGET_REGISTER_CLASS (void)
-This target hook returns a register class for which branch target register
-optimizations should be applied. All registers in this class should be
-usable interchangeably. After reload, registers in this class will be
-re-allocated and loads will be hoisted out of loops and be subjected
-to inter-block scheduling.
-@end deftypefn
-
-@deftypefn {Target Hook} bool TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED (bool @var{after_prologue_epilogue_gen})
-Branch target register optimization will by default exclude callee-saved
-registers
-that are not already live during the current function; if this target hook
-returns true, they will be included. The target code must than make sure
-that all target registers in the class returned by
-@samp{TARGET_BRANCH_TARGET_REGISTER_CLASS} that might need saving are
-saved. @var{after_prologue_epilogue_gen} indicates if prologues and
-epilogues have already been generated. Note, even if you only return
-true when @var{after_prologue_epilogue_gen} is false, you still are likely
-to have to make special provisions in @code{INITIAL_ELIMINATION_OFFSET}
-to reserve space for caller-saved target registers.
-@end deftypefn
-
@deftypefn {Target Hook} bool TARGET_HAVE_CONDITIONAL_EXECUTION (void)
This target hook returns true if the target supports conditional execution.
This target hook is required only when the target has several different
===================================================================
@@ -585,8 +585,6 @@ extern rtl_opt_pass *make_pass_postreloa
extern rtl_opt_pass *make_pass_postreload_cse (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_gcse2 (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_split_after_reload (gcc::context *ctxt);
-extern rtl_opt_pass *make_pass_branch_target_load_optimize1 (gcc::context
- *ctxt);
extern rtl_opt_pass *make_pass_thread_prologue_and_epilogue (gcc::context
*ctxt);
extern rtl_opt_pass *make_pass_stack_adjustments (gcc::context *ctxt);
@@ -596,8 +594,6 @@ extern rtl_opt_pass *make_pass_if_after_
extern rtl_opt_pass *make_pass_regrename (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_cprop_hardreg (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_reorder_blocks (gcc::context *ctxt);
-extern rtl_opt_pass *make_pass_branch_target_load_optimize2 (gcc::context
- *ctxt);
extern rtl_opt_pass *make_pass_leaf_regs (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_split_before_sched2 (gcc::context *ctxt);
extern rtl_opt_pass *make_pass_compare_elim_after_reload (gcc::context *ctxt);
===================================================================
@@ -461,7 +461,6 @@ along with GCC; see the file COPYING3.
NEXT_PASS (pass_split_after_reload);
NEXT_PASS (pass_ree);
NEXT_PASS (pass_compare_elim_after_reload);
- NEXT_PASS (pass_branch_target_load_optimize1);
NEXT_PASS (pass_thread_prologue_and_epilogue);
NEXT_PASS (pass_rtl_dse2);
NEXT_PASS (pass_stack_adjustments);
@@ -474,7 +473,6 @@ along with GCC; see the file COPYING3.
NEXT_PASS (pass_cprop_hardreg);
NEXT_PASS (pass_fast_rtl_dce);
NEXT_PASS (pass_reorder_blocks);
- NEXT_PASS (pass_branch_target_load_optimize2);
NEXT_PASS (pass_leaf_regs);
NEXT_PASS (pass_split_before_sched2);
NEXT_PASS (pass_sched2);
===================================================================
@@ -164,7 +164,6 @@ extern rtx default_internal_arg_pointer
extern rtx default_static_chain (const_tree, bool);
extern void default_trampoline_init (rtx, tree, rtx);
extern poly_int64 default_return_pops_args (tree, tree, poly_int64);
-extern reg_class_t default_branch_target_register_class (void);
extern reg_class_t default_ira_change_pseudo_allocno_class (int, reg_class_t,
reg_class_t);
extern bool default_lra_p (void);
===================================================================
@@ -1054,12 +1054,6 @@ default_return_pops_args (tree, tree, po
}
reg_class_t
-default_branch_target_register_class (void)
-{
- return NO_REGS;
-}
-
-reg_class_t
default_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED,
reg_class_t cl,
reg_class_t best_cl ATTRIBUTE_UNUSED)
===================================================================
@@ -307,7 +307,6 @@ test_completion_valid_options (option_pr
"-Wassign-intercept",
"-Wno-format-security",
"-fno-sched-stalled-insns",
- "-fbtr-bb-exclusive",
"-fno-tree-tail-merge",
"-Wlong-long",
"-Wno-unused-but-set-parameter",