From patchwork Mon Sep 9 11:21:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1159682 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-508604-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="iGwXLRDn"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Rm2y2f3kz9s7T for ; Mon, 9 Sep 2019 21:21:59 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=ym2UDqR4OQ5ZQtp06loTKmnVgxevoEJzCHMlVHR6gox7+F8AVIgWY eK/TrGhflrK0VNqLejMk1WaEUVsw/mzewOklh2uooYKkfoYuJDbARm4E022C9GrM 4m0oy3PEeYnpWYQXkU150hNkYS1/xd4BtducbfkDHpa95KDHDzQHo8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=G1S8vD4Kp03r3Xh14nzJ/Q05S04=; b=iGwXLRDn97LdtUPQ6zfY A1wCSs3zJBErPlqA1+mDAITf3b8jHwNqarBXdtbXIX5y9phiBgh1BM6CUhxSm4q7 kVCDGReBlPn3r7Uvq5Rq3f5HneuKLjmT8EXScI1N3VCK8uyjKHaJzPIqqXtQfkCp Ac3QtqH/U8NSdEscugVnjqM= Received: (qmail 30051 invoked by alias); 9 Sep 2019 11:21:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 29649 invoked by uid 89); 9 Sep 2019 11:21:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Sep 2019 11:21:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C287B28 for ; Mon, 9 Sep 2019 04:21:43 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 689893F71F for ; Mon, 9 Sep 2019 04:21:43 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: Remove bt-load.c Date: Mon, 09 Sep 2019 12:21:42 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes bt-load.c has AFAIK been dead code since the removal of the SH5 port in 2016. I have a patch series that would need to update the liveness tracking in a nontrivial way, so it seemed better to remove the pass rather than install an untested and probably bogus change. Tested on aarch64-linux-gnu, x86_64-linux-gnu and by cross-building one target for each CPU directory. OK to install? Richard 2019-09-09 Richard Sandiford gcc/ * Makefile.in (OBJS): Remove bt-load.o. * doc/invoke.texi (fbranch-target-load-optimize): Delete. (fbranch-target-load-optimize2, fbtr-bb-exclusive): Likewise. * common.opt (fbranch-target-load-optimize): Mark as Ignore and document that the option no longer does anything. (fbranch-target-load-optimize2, fbtr-bb-exclusive): Likewise. * target.def (branch_target_register_class): Delete. (branch_target_register_callee_saved): Likewise. * doc/tm.texi.in (TARGET_BRANCH_TARGET_REGISTER_CLASS): Likewise. (TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED): Likewise. * doc/tm.texi: Regenerate. * tree-pass.h (make_pass_branch_target_load_optimize1): Delete. (make_pass_branch_target_load_optimize2): Likewise. * passes.def (pass_branch_target_load_optimize1): Likewise. (pass_branch_target_load_optimize2): Likewise. * targhooks.h (default_branch_target_register_class): Likewise. * targhooks.c (default_branch_target_register_class): Likewise. * opt-suggestions.c (test_completion_valid_options): Remove -fbtr-bb-exclusive from the list of test options. * bt-load.c: Remove. Index: gcc/bt-load.c =================================================================== --- gcc/bt-load.c 2019-07-01 09:37:05.784536512 +0100 +++ /dev/null 2019-07-30 08:53:31.317691683 +0100 Index: gcc/Makefile.in =================================================================== --- gcc/Makefile.in 2019-09-09 12:19:41.357572457 +0100 +++ gcc/Makefile.in 2019-09-09 12:20:07.085390926 +0100 @@ -1241,7 +1241,6 @@ OBJS = \ auto-profile.o \ bb-reorder.o \ bitmap.o \ - bt-load.o \ builtins.o \ caller-save.o \ calls.o \ Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi 2019-09-09 12:19:39.289587049 +0100 +++ gcc/doc/invoke.texi 2019-09-09 12:20:07.093390870 +0100 @@ -406,8 +406,7 @@ Objective-C and Objective-C++ Dialects}. -falign-loops[=@var{n}[:@var{m}:[@var{n2}[:@var{m2}]]]] @gol -fassociative-math -fauto-profile -fauto-profile[=@var{path}] @gol -fauto-inc-dec -fbranch-probabilities @gol --fbranch-target-load-optimize -fbranch-target-load-optimize2 @gol --fbtr-bb-exclusive -fcaller-saves @gol +-fcaller-saves @gol -fcombine-stack-adjustments -fconserve-stack @gol -fcompare-elim -fcprop-registers -fcrossjumping @gol -fcse-follow-jumps -fcse-skip-blocks -fcx-fortran-rules @gol @@ -11025,24 +11024,6 @@ locations inside a translation unit sinc link time. An example of such an optimization is relaxing calls to short call instructions. -@item -fbranch-target-load-optimize -@opindex fbranch-target-load-optimize -Perform branch target register load optimization before prologue / epilogue -threading. -The use of target registers can typically be exposed only during reload, -thus hoisting loads out of loops and doing inter-block scheduling needs -a separate optimization pass. - -@item -fbranch-target-load-optimize2 -@opindex fbranch-target-load-optimize2 -Perform branch target register load optimization after prologue / epilogue -threading. - -@item -fbtr-bb-exclusive -@opindex fbtr-bb-exclusive -When performing branch target register load optimization, don't reuse -branch target registers within any basic block. - @item -fstdarg-opt @opindex fstdarg-opt Optimize the prologue of variadic argument functions with respect to usage of Index: gcc/common.opt =================================================================== --- gcc/common.opt 2019-08-25 19:10:35.538157161 +0100 +++ gcc/common.opt 2019-09-09 12:20:07.089390898 +0100 @@ -1076,16 +1076,16 @@ Common Report Var(flag_branch_probabilit Use profiling information for branch probabilities. fbranch-target-load-optimize -Common Report Var(flag_branch_target_load_optimize) Optimization -Perform branch target load optimization before prologue / epilogue threading. +Common Ignore +Does nothing. Preserved for backward compatibility. fbranch-target-load-optimize2 -Common Report Var(flag_branch_target_load_optimize2) Optimization -Perform branch target load optimization after prologue / epilogue threading. +Common Ignore +Does nothing. Preserved for backward compatibility. fbtr-bb-exclusive -Common Report Var(flag_btr_bb_exclusive) Optimization -Restrict target load migration not to re-use registers in any basic block. +Common Ignore +Does nothing. Preserved for backward compatibility. fcall-saved- Common Joined RejectNegative Var(common_deferred_options) Defer Index: gcc/target.def =================================================================== --- gcc/target.def 2019-09-05 08:49:26.265772215 +0100 +++ gcc/target.def 2019-09-09 12:20:07.101390813 +0100 @@ -2597,38 +2597,6 @@ DEFHOOK bool, (const rtx_insn *follower, const rtx_insn *followee), hook_bool_const_rtx_insn_const_rtx_insn_true) -/* Return a register class for which branch target register - optimizations should be applied. */ -DEFHOOK -(branch_target_register_class, - "This target hook returns a register class for which branch target register\n\ -optimizations should be applied. All registers in this class should be\n\ -usable interchangeably. After reload, registers in this class will be\n\ -re-allocated and loads will be hoisted out of loops and be subjected\n\ -to inter-block scheduling.", - reg_class_t, (void), - default_branch_target_register_class) - -/* Return true if branch target register optimizations should include - callee-saved registers that are not already live during the current - function. AFTER_PE_GEN is true if prologues and epilogues have - already been generated. */ -DEFHOOK -(branch_target_register_callee_saved, - "Branch target register optimization will by default exclude callee-saved\n\ -registers\n\ -that are not already live during the current function; if this target hook\n\ -returns true, they will be included. The target code must than make sure\n\ -that all target registers in the class returned by\n\ -@samp{TARGET_BRANCH_TARGET_REGISTER_CLASS} that might need saving are\n\ -saved. @var{after_prologue_epilogue_gen} indicates if prologues and\n\ -epilogues have already been generated. Note, even if you only return\n\ -true when @var{after_prologue_epilogue_gen} is false, you still are likely\n\ -to have to make special provisions in @code{INITIAL_ELIMINATION_OFFSET}\n\ -to reserve space for caller-saved target registers.", - bool, (bool after_prologue_epilogue_gen), - hook_bool_bool_false) - /* Return true if the target supports conditional execution. */ DEFHOOK (have_conditional_execution, Index: gcc/doc/tm.texi.in =================================================================== --- gcc/doc/tm.texi.in 2019-09-05 08:49:25.753775874 +0100 +++ gcc/doc/tm.texi.in 2019-09-09 12:20:07.097390842 +0100 @@ -8001,10 +8001,6 @@ build_type_attribute_variant (@var{mdecl @hook TARGET_CANNOT_MODIFY_JUMPS_P -@hook TARGET_BRANCH_TARGET_REGISTER_CLASS - -@hook TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED - @hook TARGET_HAVE_CONDITIONAL_EXECUTION @hook TARGET_GEN_CCMP_FIRST Index: gcc/doc/tm.texi =================================================================== --- gcc/doc/tm.texi 2019-09-05 08:49:25.753775874 +0100 +++ gcc/doc/tm.texi 2019-09-09 12:20:07.097390842 +0100 @@ -11755,28 +11755,6 @@ cannot_modify_jumps_past_reload_p () @end smallexample @end deftypefn -@deftypefn {Target Hook} reg_class_t TARGET_BRANCH_TARGET_REGISTER_CLASS (void) -This target hook returns a register class for which branch target register -optimizations should be applied. All registers in this class should be -usable interchangeably. After reload, registers in this class will be -re-allocated and loads will be hoisted out of loops and be subjected -to inter-block scheduling. -@end deftypefn - -@deftypefn {Target Hook} bool TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED (bool @var{after_prologue_epilogue_gen}) -Branch target register optimization will by default exclude callee-saved -registers -that are not already live during the current function; if this target hook -returns true, they will be included. The target code must than make sure -that all target registers in the class returned by -@samp{TARGET_BRANCH_TARGET_REGISTER_CLASS} that might need saving are -saved. @var{after_prologue_epilogue_gen} indicates if prologues and -epilogues have already been generated. Note, even if you only return -true when @var{after_prologue_epilogue_gen} is false, you still are likely -to have to make special provisions in @code{INITIAL_ELIMINATION_OFFSET} -to reserve space for caller-saved target registers. -@end deftypefn - @deftypefn {Target Hook} bool TARGET_HAVE_CONDITIONAL_EXECUTION (void) This target hook returns true if the target supports conditional execution. This target hook is required only when the target has several different Index: gcc/tree-pass.h =================================================================== --- gcc/tree-pass.h 2019-08-27 07:24:48.647533197 +0100 +++ gcc/tree-pass.h 2019-09-09 12:20:07.101390813 +0100 @@ -585,8 +585,6 @@ extern rtl_opt_pass *make_pass_postreloa extern rtl_opt_pass *make_pass_postreload_cse (gcc::context *ctxt); extern rtl_opt_pass *make_pass_gcse2 (gcc::context *ctxt); extern rtl_opt_pass *make_pass_split_after_reload (gcc::context *ctxt); -extern rtl_opt_pass *make_pass_branch_target_load_optimize1 (gcc::context - *ctxt); extern rtl_opt_pass *make_pass_thread_prologue_and_epilogue (gcc::context *ctxt); extern rtl_opt_pass *make_pass_stack_adjustments (gcc::context *ctxt); @@ -596,8 +594,6 @@ extern rtl_opt_pass *make_pass_if_after_ extern rtl_opt_pass *make_pass_regrename (gcc::context *ctxt); extern rtl_opt_pass *make_pass_cprop_hardreg (gcc::context *ctxt); extern rtl_opt_pass *make_pass_reorder_blocks (gcc::context *ctxt); -extern rtl_opt_pass *make_pass_branch_target_load_optimize2 (gcc::context - *ctxt); extern rtl_opt_pass *make_pass_leaf_regs (gcc::context *ctxt); extern rtl_opt_pass *make_pass_split_before_sched2 (gcc::context *ctxt); extern rtl_opt_pass *make_pass_compare_elim_after_reload (gcc::context *ctxt); Index: gcc/passes.def =================================================================== --- gcc/passes.def 2019-08-27 07:24:49.247528903 +0100 +++ gcc/passes.def 2019-09-09 12:20:07.097390842 +0100 @@ -461,7 +461,6 @@ along with GCC; see the file COPYING3. NEXT_PASS (pass_split_after_reload); NEXT_PASS (pass_ree); NEXT_PASS (pass_compare_elim_after_reload); - NEXT_PASS (pass_branch_target_load_optimize1); NEXT_PASS (pass_thread_prologue_and_epilogue); NEXT_PASS (pass_rtl_dse2); NEXT_PASS (pass_stack_adjustments); @@ -474,7 +473,6 @@ along with GCC; see the file COPYING3. NEXT_PASS (pass_cprop_hardreg); NEXT_PASS (pass_fast_rtl_dce); NEXT_PASS (pass_reorder_blocks); - NEXT_PASS (pass_branch_target_load_optimize2); NEXT_PASS (pass_leaf_regs); NEXT_PASS (pass_split_before_sched2); NEXT_PASS (pass_sched2); Index: gcc/targhooks.h =================================================================== --- gcc/targhooks.h 2019-08-20 09:53:16.222346371 +0100 +++ gcc/targhooks.h 2019-09-09 12:20:07.101390813 +0100 @@ -164,7 +164,6 @@ extern rtx default_internal_arg_pointer extern rtx default_static_chain (const_tree, bool); extern void default_trampoline_init (rtx, tree, rtx); extern poly_int64 default_return_pops_args (tree, tree, poly_int64); -extern reg_class_t default_branch_target_register_class (void); extern reg_class_t default_ira_change_pseudo_allocno_class (int, reg_class_t, reg_class_t); extern bool default_lra_p (void); Index: gcc/targhooks.c =================================================================== --- gcc/targhooks.c 2019-08-20 09:53:27.554263904 +0100 +++ gcc/targhooks.c 2019-09-09 12:20:07.101390813 +0100 @@ -1054,12 +1054,6 @@ default_return_pops_args (tree, tree, po } reg_class_t -default_branch_target_register_class (void) -{ - return NO_REGS; -} - -reg_class_t default_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED, reg_class_t cl, reg_class_t best_cl ATTRIBUTE_UNUSED) Index: gcc/opt-suggestions.c =================================================================== --- gcc/opt-suggestions.c 2019-04-29 16:16:42.990632264 +0100 +++ gcc/opt-suggestions.c 2019-09-09 12:20:07.097390842 +0100 @@ -307,7 +307,6 @@ test_completion_valid_options (option_pr "-Wassign-intercept", "-Wno-format-security", "-fno-sched-stalled-insns", - "-fbtr-bb-exclusive", "-fno-tree-tail-merge", "-Wlong-long", "-Wno-unused-but-set-parameter",