===================================================================
@@ -2780,33 +2780,6 @@
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
-(define_insn "*extvqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m")
- (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q,Q")
- (const_int 8)
- (const_int 8)))]
- ""
-{
- switch (get_attr_type (insn))
- {
- case TYPE_IMOVX:
- return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
- default:
- return "mov{b}\t{%h1, %0|%0, %h1}";
- }
-}
- [(set_attr "isa" "*,*,nox64")
- (set (attr "type")
- (if_then_else (and (match_operand:QI 0 "register_operand")
- (ior (not (match_operand:QI 0 "QIreg_operand"))
- (match_test "TARGET_MOVX")))
- (const_string "imovx")
- (const_string "imov")))
- (set (attr "mode")
- (if_then_else (eq_attr "type" "imovx")
- (const_string "SI")
- (const_string "QI")))])
-
(define_expand "extzv<mode>"
[(set (match_operand:SWI248 0 "register_operand")
(zero_extract:SWI248 (match_operand:SWI248 1 "register_operand")
@@ -7586,7 +7559,8 @@
emit_insn (gen_divmodhiqi3 (tmp0, tmp1, operands[2]));
/* Extract remainder from AH. */
- tmp1 = gen_rtx_SIGN_EXTRACT (QImode, tmp0, GEN_INT (8), GEN_INT (8));
+ tmp1 = gen_rtx_ZERO_EXTRACT (SImode, tmp0, GEN_INT (8), GEN_INT (8));
+ tmp1 = gen_rtx_SUBREG (QImode, tmp1, 0);
rtx_insn *insn = emit_move_insn (operands[3], tmp1);
mod = gen_rtx_MOD (QImode, operands[1], operands[2]);
===================================================================
@@ -0,0 +1,21 @@
+/* PR target/78904 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -masm=att" } */
+
+typedef __SIZE_TYPE__ size_t;
+
+struct S1
+{
+ char pad1;
+ char val;
+ short pad2;
+};
+
+extern char t[256];
+
+void foo (struct S1 a, size_t i)
+{
+ t[i] = a.val;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]movb\[\t \]*%.h," } } */
Hello! Attached patch removes unneeded *extvqi sign-extract pattern. Combine is smart enough to create zero-extract RTX in case QImode value is extracted to QImode register. OTOH, the following testcase --cut here-- struct S1 { char pad1; char val; short pad2; }; struct S1 test_add (struct S1 a, struct S1 b) { a.val += b.val; return a; } --cut here-- still compiles to: movl %edi, %eax movl %esi, %ecx movsbl %ah, %edx movsbl %ch, %esi addl %esi, %edx movb %dl, %ah since combine doesn't simplify sign-extract in: Trying 7, 9 -> 10: Failed to match this instruction: (set (zero_extract:SI (reg/v:SI 95 [ a ]) (const_int 8 [0x8]) (const_int 8 [0x8])) (subreg:SI (plus:QI (subreg:QI (sign_extract:SI (reg/v:SI 95 [ a ]) (const_int 8 [0x8]) (const_int 8 [0x8])) 0) (reg:QI 98)) 0)) to a zero-extract, although we have QImode operation. This should follow the same reasoning as in the attached testcase, where: (insn 8 4 9 2 (set (reg:SI 91) (sign_extract:SI (reg/v:SI 88 [ a ]) (const_int 8 [0x8]) (const_int 8 [0x8]))) "pr78904-6.c":18 102 {*extvsi} (expr_list:REG_DEAD (reg/v:SI 88 [ a ]) (nil))) (insn 9 8 0 2 (set (mem/j:QI (plus:DI (reg/v:DI 89 [ i ]) (symbol_ref:DI ("t") [flags 0x40] <var_decl 0x7f9e35cd4e10 t>)) [0 t S1 A8]) (subreg:QI (reg:SI 91) 0)) "pr78904-6.c":18 84 {*movqi_internal} (expr_list:REG_DEAD (reg:SI 91) (expr_list:REG_DEAD (reg/v:DI 89 [ i ]) (nil)))) simplifies to Trying 8 -> 9: Successfully matched this instruction: (set (mem/j:QI (plus:DI (reg/v:DI 89 [ i ]) (symbol_ref:DI ("t") [flags 0x40] <var_decl 0x7f9e35cd4e10 t>)) [0 t S1 A8]) (subreg:QI (zero_extract:SI (reg/v:SI 88 [ a ]) (const_int 8 [0x8]) (const_int 8 [0x8])) 0)) I'll open a PR for the above combine deficiency. 2016-12-29 Uros Bizjak <ubizjak@gmail.com> PR target/78904 * config/i386/i386.md (*extvqi): Remove insn pattern. (divmodqi4): Update expander to generate QImode zero-extract from AH. testsuite/ChangeLog: 2016-12-29 Uros Bizjak <ubizjak@gmail.com> PR target/78904 * gcc.target/i386/pr78904-6.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros.