| Message ID | 20231220122732.449-1-cooper.joshua@linux.alibaba.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Support XTheadVector extension | expand |
On 12/20/23 05:27, Jun Sha (Joshua) wrote: > This patch splits the definition of csr_operand in predicates.md. > The newly defined vector_csr_operand has the same functionality > as csr_operand but can only be used in vector patterns, so that > changes for vector will not affect scalar patterns in files > like riscv.md. > > gcc/ChangeLog: > > * config/riscv/predicates.md (vector_csr_operand): > Define vector_csr_opeand for vector. > * config/riscv/vector.md: > Use newly defined csr_operand for vector. So do you envision changing something in vector_csr_operand? If not, then this doesn't make much sense. Jeff
Hi Jeff, Yes, I will change soemthing in vector_csr_operand in the following patches. Constraints will be added that the AVL cannot be encoded as an immediate for xtheadvecotr vsetvl. Joshua ------------------------------------------------------------------ 发件人：Jeff Law <jeffreyalaw@gmail.com> 发送时间：2023年12月21日(星期四) 02:16 收件人："Jun Sha (Joshua)"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org> 抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; "christoph.muellner"<christoph.muellner@vrull.eu>; "juzhe.zhong"<juzhe.zhong@rivai.ai>; Jin Ma<jinma@linux.alibaba.com>; Xianmiao Qu<cooper.qu@linux.alibaba.com> 主 题：Re: [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns. On 12/20/23 05:27, Jun Sha (Joshua) wrote: > This patch splits the definition of csr_operand in predicates.md. > The newly defined vector_csr_operand has the same functionality > as csr_operand but can only be used in vector patterns, so that > changes for vector will not affect scalar patterns in files > like riscv.md. > > gcc/ChangeLog: > > * config/riscv/predicates.md (vector_csr_operand): > Define vector_csr_opeand for vector. > * config/riscv/vector.md: > Use newly defined csr_operand for vector. So do you envision changing something in vector_csr_operand? If not, then this doesn't make much sense. Jeff
On 12/26/23 19:49, joshua wrote: > Hi Jeff, > > Yes, I will change soemthing in vector_csr_operand in the following > patches. > > Constraints will be added that the AVL cannot be encoded as an > immediate for xtheadvecotr vsetvl. Ah. Thanks. Makes sense. jeff
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 6bf6e186641..1a3a4f1ecbb 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -63,6 +63,10 @@ (define_predicate "csr_operand" (ior (match_operand 0 "const_csr_operand") (match_operand 0 "register_operand"))) +(define_predicate "vector_csr_operand" + (ior (match_operand 0 "const_csr_operand") + (match_operand 0 "register_operand"))) + ;; V has 32-bit unsigned immediates. This happens to be the same constraint as ;; the csr_operand, but it's not CSR related. (define_predicate "vector_scalar_shift_operand" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f607d768b26..036b2425f32 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1496,7 +1496,7 @@ (define_insn_and_split "*vec_duplicate<mode>" (define_insn "@vsetvl<mode>" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (unspec:P [(match_operand:P 1 "vector_csr_operand" "rK") (match_operand 2 "const_int_operand" "i") (match_operand 3 "const_int_operand" "i") (match_operand 4 "const_int_operand" "i") @@ -1542,7 +1542,7 @@ (define_insn "vsetvl_vtype_change_only" ;; in vsetvl instruction pattern. (define_insn "@vsetvl_discard_result<mode>" [(set (reg:SI VL_REGNUM) - (unspec:SI [(match_operand:P 0 "csr_operand" "rK") + (unspec:SI [(match_operand:P 0 "vector_csr_operand" "rK") (match_operand 1 "const_int_operand" "i") (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL)) (set (reg:SI VTYPE_REGNUM) @@ -1564,7 +1564,7 @@ (define_insn "@vsetvl_discard_result<mode>" ;; such pattern can allow us gain benefits of these optimizations. (define_insn_and_split "@vsetvl<mode>_no_side_effects" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (unspec:P [(match_operand:P 1 "vector_csr_operand" "rK") (match_operand 2 "const_int_operand" "i") (match_operand 3 "const_int_operand" "i") (match_operand 4 "const_int_operand" "i") @@ -1608,7 +1608,7 @@ (define_insn_and_split "*vsetvldi_no_side_effects_si_extend" [(set (match_operand:DI 0 "register_operand") (sign_extend:DI (subreg:SI - (unspec:DI [(match_operand:P 1 "csr_operand") + (unspec:DI [(match_operand:P 1 "vector_csr_operand") (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand") (match_operand 4 "const_int_operand")