| Message ID | 20231220122055.343-1-cooper.joshua@linux.alibaba.com |
|---|---|
| Headers | show |
| Series | RISC-V: Support XTheadVector extension | expand |
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out the better way to do that (Current this patch with copying patterns is not approach I like)
So, I hope you can break this big patch into 3 different series patches.
1. Support partial theadvector instructions which leverage directly from current RVV1.0 with simple adding "th." prefix.
2. Support totally different name theadvector instructions but share same patterns as RVV1.0 instructions.
3. Support new headvector instructions like vlib...etc.
I think 1 and 3 separate patches can be quickly merged after my more details reviewed and approved in the following patches you send like V4 ?.
For 2, it's a bit more complicate, but I think we can support like ARM and other targets, use ASM targethook to rewrite the whole string of the instructions.
For example, like strided load/store, you can know this instructions from attribute:
(set_attr "type" "vlds")
juzhe.zhong@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-20 20:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html
Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples,
and all the tests passed.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
---
gcc/common/config/riscv/riscv-common.cc | 23 +
gcc/config.gcc | 4 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 8 +-
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string.cc | 3 +
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 18 +-
.../riscv/riscv-vector-builtins-bases.h | 19 +
.../riscv/riscv-vector-builtins-shapes.cc | 149 +
.../riscv/riscv-vector-builtins-shapes.h | 3 +
.../riscv/riscv-vector-builtins-types.def | 120 +
gcc/config/riscv/riscv-vector-builtins.cc | 315 +-
gcc/config/riscv/riscv-vector-builtins.h | 5 +-
gcc/config/riscv/riscv-vector-switch.def | 150 +-
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/riscv_th_vector.h | 49 +
gcc/config/riscv/t-riscv | 16 +
.../riscv/thead-vector-builtins-functions.def | 659 ++++
gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++
gcc/config/riscv/thead-vector-builtins.h | 123 +
gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++
gcc/config/riscv/vector-iterators.md | 186 +-
gcc/config/riscv/vector.md | 44 +-
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
.../gcc.target/riscv/rvv/base/abi-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
.../gcc.target/riscv/rvv/xtheadvector.c | 13 +
.../riscv/rvv/xtheadvector/prefix.c | 12 +
.../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +
gcc/testsuite/lib/target-supports.exp | 12 +
39 files changed, 5931 insertions(+), 213 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins.h
create mode 100644 gcc/config/riscv/thead-vector.md
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
Btw, rv32/rv64gc or rv32/rv64 gcv testing is not enough.
We need full coverage testing, since we always commit patch after no regression testing on full coverage testing:
with these following configurations:
-march=rv[32/64]gc_zve32f_zvfh_zfh
-march=rv[32/64]gc_zve64d_zvfh_zfh
-march=rv[32/64]gcv_zvfh_zfh
-march=rv[32/64]gcv_zvl256b_zvfh_zfh
-march=rv[32/64]gcv_zvl512b_zvfh_zfh
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-lmul=m2
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-lmul=m4
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-lmul=m8
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-lmul=dynamic
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-lmul=m2
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-lmul=m4
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-lmul=m8
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-lmul=dynamic
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-lmul=m2
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-lmul=m4
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-lmul=m8
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-lmul=dynamic
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-lmul=m2
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-lmul=m4
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-lmul=m8
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-lmul=dynamic
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-lmul=m2
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-lmul=m4
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-lmul=m8
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-lmul=dynamic
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-lmul=m2
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-lmul=m4
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-lmul=m8
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-lmul=dynamic
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve32f_zvfh_zfh --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gc_zve64d_zvfh_zfh --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvfh_zfh --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl256b_zvfh_zfh --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl512b_zvfh_zfh --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax
-march=rv[32/64]gcv_zvl1024b_zvfh_zfh --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax
You can learn more how to run these testing with email to pan2.li@intel.com
juzhe.zhong@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-20 20:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html
Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples,
and all the tests passed.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
---
gcc/common/config/riscv/riscv-common.cc | 23 +
gcc/config.gcc | 4 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 8 +-
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string.cc | 3 +
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 18 +-
.../riscv/riscv-vector-builtins-bases.h | 19 +
.../riscv/riscv-vector-builtins-shapes.cc | 149 +
.../riscv/riscv-vector-builtins-shapes.h | 3 +
.../riscv/riscv-vector-builtins-types.def | 120 +
gcc/config/riscv/riscv-vector-builtins.cc | 315 +-
gcc/config/riscv/riscv-vector-builtins.h | 5 +-
gcc/config/riscv/riscv-vector-switch.def | 150 +-
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/riscv_th_vector.h | 49 +
gcc/config/riscv/t-riscv | 16 +
.../riscv/thead-vector-builtins-functions.def | 659 ++++
gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++
gcc/config/riscv/thead-vector-builtins.h | 123 +
gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++
gcc/config/riscv/vector-iterators.md | 186 +-
gcc/config/riscv/vector.md | 44 +-
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
.../gcc.target/riscv/rvv/base/abi-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
.../gcc.target/riscv/rvv/xtheadvector.c | 13 +
.../riscv/rvv/xtheadvector/prefix.c | 12 +
.../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +
gcc/testsuite/lib/target-supports.exp | 12 +
39 files changed, 5931 insertions(+), 213 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins.h
create mode 100644 gcc/config/riscv/thead-vector.md
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
On 12/20/23 16:08, 钟居哲 wrote: > Btw, rv32/rv64gc or rv32/rv64 gcv testing is not enough. > > We need full coverage testing, since we always commit patch after no > regression testing on full coverage testing: No. It is unreasonable to require this large of test matrix for the vast majority if contributions. thead should be able to pick a reasonable set that provides a degree of coverage, but they don't need to test all those configurations. jeff
OK. Sounds reasonable. But from my side, I used to commit patches after full coverage testing. juzhe.zhong@rivai.ai From: Jeff Law Date: 2023-12-21 11:28 To: 钟居哲; cooper.joshua; gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu Subject: Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension On 12/20/23 16:08, 钟居哲 wrote: > Btw, rv32/rv64gc or rv32/rv64 gcv testing is not enough. > > We need full coverage testing, since we always commit patch after no > regression testing on full coverage testing: No. It is unreasonable to require this large of test matrix for the vast majority if contributions. thead should be able to pick a reasonable set that provides a degree of coverage, but they don't need to test all those configurations. jeff
On 12/20/23 20:30, juzhe.zhong@rivai.ai wrote: > OK. Sounds reasonable. > > But from my side, I used to commit patches after full coverage testing. Understood. And it's appreciated -- the code you're doing hits a wide variety of configurations, so the wider testing is probably applicable. Ideally the thead vector bits need reasonable testing to make sure they don't totally break the standard RVV support. So for something like the final scheme to add the "th." prefix I'd expect they can get away with just rv64gcv. WHile there is a chance that'll miss something, the odds are pretty low that a bug will be uncovered for each additional configuration tested beyond the first. In contrast if they needed to make a structural changes that are more than adding a path for thead's vector unit, then we might reasonably ask for a deeper test of that specific patch (perhaps even suggesting the configurations most likely affected and thus which need to be tested). The key being we want to use time wisely and testing dozens of multilibs for each change isn't really reasonable. It's always a delicate balance to articulate the right level of testing because the "right" level can vary based on each engineer's risk assessment of a particular change. Jeff
Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our patchset more organized.
For 1) and 3), I will split out the patches soon and hope they will be merged quickly.
For 2), according to the differences between vector and xtheadvector, it can be classfied into 3 kinds.
First is renamed load/store, renamed narrowing integer right shift, renamed narrowing fixed-point clip, and etc. I think we can use ASM targethook to rewrite the whole string of the instructions, although it will still be a heavy work.
Second is no pseudo instruction like vneg/vfneg. We will add these pseudo instructions in binutils to make xtheadvector more compatible with vector.
Third is that destination vector register cannot overlap source vector register group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot come up with any better way than pattern copy. Do you have any suggestions?
Joshua
------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; Jeff Law<jeffreyalaw@gmail.com>; "Christoph Müllner"<christoph.muellner@vrull.eu>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主 题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out the better way to do that (Current this patch with copying patterns is not approach I like)
So, I hope you can break this big patch into 3 different series patches.
1. Support partial theadvector instructions which leverage directly from current RVV1.0 with simple adding "th." prefix.
2. Support totally different name theadvector instructions but share same patterns as RVV1.0 instructions.
3. Support new headvector instructions like vlib...etc.
I think 1 and 3 separate patches can be quickly merged after my more details reviewed and approved in the following patches you send like V4 ?.
For 2, it's a bit more complicate, but I think we can support like ARM and other targets, use ASM targethook to rewrite the whole string of the instructions.
For example, like strided load/store, you can know this instructions from attribute:
(set_attr "type" "vlds")
juzhe.zhong@rivai.ai
From: Jun Sha (Joshua) <mailto:cooper.joshua@linux.alibaba.com >
Date: 2023-12-20 20:20
To: gcc-patches <mailto:gcc-patches@gcc.gnu.org >
CC: jim.wilson.gcc <mailto:jim.wilson.gcc@gmail.com >; palmer <mailto:palmer@dabbelt.com >; andrew <mailto:andrew@sifive.com >; philipp.tomsich <mailto:philipp.tomsich@vrull.eu >; jeffreyalaw <mailto:jeffreyalaw@gmail.com >; christoph.muellner <mailto:christoph.muellner@vrull.eu >; juzhe.zhong <mailto:juzhe.zhong@rivai.ai >; Jun Sha (Joshua) <mailto:cooper.joshua@linux.alibaba.com >; Jin Ma <mailto:jinma@linux.alibaba.com >; Xianmiao Qu <mailto:cooper.qu@linux.alibaba.com >
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/ <https://github.com/T-head-Semi/thead-extension-spec/ >
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html <https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html >
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html <https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html >
Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples <https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples >,
and all the tests passed.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
---
gcc/common/config/riscv/riscv-common.cc | 23 +
gcc/config.gcc | 4 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 8 +-
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string.cc | 3 +
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 18 +-
.../riscv/riscv-vector-builtins-bases.h | 19 +
.../riscv/riscv-vector-builtins-shapes.cc | 149 +
.../riscv/riscv-vector-builtins-shapes.h | 3 +
.../riscv/riscv-vector-builtins-types.def | 120 +
gcc/config/riscv/riscv-vector-builtins.cc | 315 +-
gcc/config/riscv/riscv-vector-builtins.h | 5 +-
gcc/config/riscv/riscv-vector-switch.def | 150 +-
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/riscv_th_vector.h | 49 +
gcc/config/riscv/t-riscv | 16 +
.../riscv/thead-vector-builtins-functions.def | 659 ++++
gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++
gcc/config/riscv/thead-vector-builtins.h | 123 +
gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++
gcc/config/riscv/vector-iterators.md | 186 +-
gcc/config/riscv/vector.md | 44 +-
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
.../gcc.target/riscv/rvv/base/abi-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
.../gcc.target/riscv/rvv/xtheadvector.c | 13 +
.../riscv/rvv/xtheadvector/prefix.c | 12 +
.../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +
gcc/testsuite/lib/target-supports.exp | 12 +
39 files changed, 5931 insertions(+), 213 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins.h
create mode 100644 gcc/config/riscv/thead-vector.md
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
You mean theadvector doesn't want the current RVV1.0 register overlap magic as follows ?
The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).
The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).
If yes, I suggest disable the overlap constraint using attribute, More details you can learn from
(set_attr "group_overlap"
juzhe.zhong@rivai.ai
发件人： joshua
发送时间： 2023-12-22 11:33
收件人： 钟居哲; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Jeff Law; Christoph Müllner; jinma; Cooper Qu
主题： 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our patchset more organized.
For 1) and 3), I will split out the patches soon and hope they will be merged quickly.
For 2), according to the differences between vector and xtheadvector, it can be classfied into 3 kinds.
First is renamed load/store, renamed narrowing integer right shift, renamed narrowing fixed-point clip, and etc. I think we can use ASM targethook to rewrite the whole string of the instructions, although it will still be a heavy work.
Second is no pseudo instruction like vneg/vfneg. We will add these pseudo instructions in binutils to make xtheadvector more compatible with vector.
Third is that destination vector register cannot overlap source vector register group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot come up with any better way than pattern copy. Do you have any suggestions?
Joshua
------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; Jeff Law<jeffreyalaw@gmail.com>; "Christoph Müllner"<christoph.muellner@vrull.eu>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主 题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out the better way to do that (Current this patch with copying patterns is not approach I like)
So, I hope you can break this big patch into 3 different series patches.
1. Support partial theadvector instructions which leverage directly from current RVV1.0 with simple adding "th." prefix.
2. Support totally different name theadvector instructions but share same patterns as RVV1.0 instructions.
3. Support new headvector instructions like vlib...etc.
I think 1 and 3 separate patches can be quickly merged after my more details reviewed and approved in the following patches you send like V4 ?.
For 2, it's a bit more complicate, but I think we can support like ARM and other targets, use ASM targethook to rewrite the whole string of the instructions.
For example, like strided load/store, you can know this instructions from attribute:
(set_attr "type" "vlds")
juzhe.zhong@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-20 20:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html
Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples,
and all the tests passed.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
---
gcc/common/config/riscv/riscv-common.cc | 23 +
gcc/config.gcc | 4 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 8 +-
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string.cc | 3 +
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 18 +-
.../riscv/riscv-vector-builtins-bases.h | 19 +
.../riscv/riscv-vector-builtins-shapes.cc | 149 +
.../riscv/riscv-vector-builtins-shapes.h | 3 +
.../riscv/riscv-vector-builtins-types.def | 120 +
gcc/config/riscv/riscv-vector-builtins.cc | 315 +-
gcc/config/riscv/riscv-vector-builtins.h | 5 +-
gcc/config/riscv/riscv-vector-switch.def | 150 +-
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/riscv_th_vector.h | 49 +
gcc/config/riscv/t-riscv | 16 +
.../riscv/thead-vector-builtins-functions.def | 659 ++++
gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++
gcc/config/riscv/thead-vector-builtins.h | 123 +
gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++
gcc/config/riscv/vector-iterators.md | 186 +-
gcc/config/riscv/vector.md | 44 +-
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
.../gcc.target/riscv/rvv/base/abi-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
.../gcc.target/riscv/rvv/xtheadvector.c | 13 +
.../riscv/rvv/xtheadvector/prefix.c | 12 +
.../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +
gcc/testsuite/lib/target-supports.exp | 12 +
39 files changed, 5931 insertions(+), 213 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins.h
create mode 100644 gcc/config/riscv/thead-vector.md
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
Hi Juzhe,
What xtheadvector needs to handle is just that destination vector register cannot overlap source vector register group for instructions like vmadc/vmsbc. That is not what group_overlap means. We nned to add "&" to the registers in the corresponding xtheadvector patterns while rvv 1.0 doesn't have this constraint.
(define_insn "@pred_th_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=&vr")
(unspec:<VM>
[(minus:VI
(match_operand:VI 1 "register_operand" " vr")
(match_operand:VI 2 "register_operand" " vr"))
(match_operand:<VM> 3 "register_operand" " vm")
(unspec:<VM>
[(match_operand 4 "vector_length_operand" " rK")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_XTHEADVECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
(set (attr "avl_type_idx") (const_int 5))])
Joshua
------------------------------------------------------------------
发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
发送时间：2023年12月22日(星期五) 16:07
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; jeffreyalaw<jeffreyalaw@gmail.com>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主 题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
You mean theadvector doesn't want the current RVV1.0 register overlap magic as follows ?
*
The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).
*
The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).
If yes, I suggest disable the overlap constraint using attribute, More details you can learn from
(set_attr "group_overlap"
juzhe.zhong@rivai.ai
发件人： joshua <mailto:cooper.joshua@linux.alibaba.com >
发送时间： 2023-12-22 11:33
收件人： 钟居哲 <mailto:juzhe.zhong@rivai.ai >; gcc-patches <mailto:gcc-patches@gcc.gnu.org >
抄送： jim.wilson.gcc <mailto:jim.wilson.gcc@gmail.com >; palmer <mailto:palmer@dabbelt.com >; andrew <mailto:andrew@sifive.com >; philipp.tomsich <mailto:philipp.tomsich@vrull.eu >; Jeff Law <mailto:jeffreyalaw@gmail.com >; Christoph Müllner <mailto:christoph.muellner@vrull.eu >; jinma <mailto:jinma@linux.alibaba.com >; Cooper Qu <mailto:cooper.qu@linux.alibaba.com >
主题： 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our patchset more organized.
For 1) and 3), I will split out the patches soon and hope they will be merged quickly.
For 2), according to the differences between vector and xtheadvector, it can be classfied into 3 kinds.
First is renamed load/store, renamed narrowing integer right shift, renamed narrowing fixed-point clip, and etc. I think we can use ASM targethook to rewrite the whole string of the instructions, although it will still be a heavy work.
Second is no pseudo instruction like vneg/vfneg. We will add these pseudo instructions in binutils to make xtheadvector more compatible with vector.
Third is that destination vector register cannot overlap source vector register group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot come up with any better way than pattern copy. Do you have any suggestions?
Joshua
------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; Jeff Law<jeffreyalaw@gmail.com>; "Christoph Müllner"<christoph.muellner@vrull.eu>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主 题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out the better way to do that (Current this patch with copying patterns is not approach I like)
So, I hope you can break this big patch into 3 different series patches.
1. Support partial theadvector instructions which leverage directly from current RVV1.0 with simple adding "th." prefix.
2. Support totally different name theadvector instructions but share same patterns as RVV1.0 instructions.
3. Support new headvector instructions like vlib...etc.
I think 1 and 3 separate patches can be quickly merged after my more details reviewed and approved in the following patches you send like V4 ?.
For 2, it's a bit more complicate, but I think we can support like ARM and other targets, use ASM targethook to rewrite the whole string of the instructions.
For example, like strided load/store, you can know this instructions from attribute:
(set_attr "type" "vlds")
juzhe.zhong@rivai.ai
From: Jun Sha (Joshua) <mailto:cooper.joshua@linux.alibaba.com >
Date: 2023-12-20 20:20
To: gcc-patches <mailto:gcc-patches@gcc.gnu.org >
CC: jim.wilson.gcc <mailto:jim.wilson.gcc@gmail.com >; palmer <mailto:palmer@dabbelt.com >; andrew <mailto:andrew@sifive.com >; philipp.tomsich <mailto:philipp.tomsich@vrull.eu >; jeffreyalaw <mailto:jeffreyalaw@gmail.com >; christoph.muellner <mailto:christoph.muellner@vrull.eu >; juzhe.zhong <mailto:juzhe.zhong@rivai.ai >; Jun Sha (Joshua) <mailto:cooper.joshua@linux.alibaba.com >; Jin Ma <mailto:jinma@linux.alibaba.com >; Xianmiao Qu <mailto:cooper.qu@linux.alibaba.com >
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/ <https://github.com/T-head-Semi/thead-extension-spec/ >
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html <https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html >
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html <https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html >
Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples <https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples >,
and all the tests passed.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
---
gcc/common/config/riscv/riscv-common.cc | 23 +
gcc/config.gcc | 4 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 8 +-
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string.cc | 3 +
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 18 +-
.../riscv/riscv-vector-builtins-bases.h | 19 +
.../riscv/riscv-vector-builtins-shapes.cc | 149 +
.../riscv/riscv-vector-builtins-shapes.h | 3 +
.../riscv/riscv-vector-builtins-types.def | 120 +
gcc/config/riscv/riscv-vector-builtins.cc | 315 +-
gcc/config/riscv/riscv-vector-builtins.h | 5 +-
gcc/config/riscv/riscv-vector-switch.def | 150 +-
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/riscv_th_vector.h | 49 +
gcc/config/riscv/t-riscv | 16 +
.../riscv/thead-vector-builtins-functions.def | 659 ++++
gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++
gcc/config/riscv/thead-vector-builtins.h | 123 +
gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++
gcc/config/riscv/vector-iterators.md | 186 +-
gcc/config/riscv/vector.md | 44 +-
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
.../gcc.target/riscv/rvv/base/abi-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
.../gcc.target/riscv/rvv/xtheadvector.c | 13 +
.../riscv/rvv/xtheadvector/prefix.c | 12 +
.../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +
gcc/testsuite/lib/target-supports.exp | 12 +
39 files changed, 5931 insertions(+), 213 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins.h
create mode 100644 gcc/config/riscv/thead-vector.md
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
Yeah.
(define_insn "@pred_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
(unspec:<VM>
[(minus:VI
(match_operand:VI 1 "register_operand" " 0, vr, vr")
(match_operand:VI 2 "register_operand" " vr, 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm, vm")
(unspec:<VM>
[(match_operand 4 "vector_length_operand" " rK, rK, rK")
(match_operand 5 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_VECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
(set (attr "avl_type_idx") (const_int 5))])
You should use an attribute to disable alternative 0 and alternative 1 constraint.
juzhe.zhong@rivai.ai
发件人： joshua
发送时间： 2023-12-22 18:29
收件人： juzhe.zhong@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu
主题： 回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
What xtheadvector needs to handle is just that destination vector register cannot overlap source vector register group for instructions like vmadc/vmsbc. That is not what group_overlap means. We nned to add "&" to the registers in the corresponding xtheadvector patterns while rvv 1.0 doesn't have this constraint.
(define_insn "@pred_th_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=&vr")
(unspec:<VM>
[(minus:VI
(match_operand:VI 1 "register_operand" " vr")
(match_operand:VI 2 "register_operand" " vr"))
(match_operand:<VM> 3 "register_operand" " vm")
(unspec:<VM>
[(match_operand 4 "vector_length_operand" " rK")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_XTHEADVECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
(set (attr "avl_type_idx") (const_int 5))])
Joshua
------------------------------------------------------------------
发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
发送时间：2023年12月22日(星期五) 16:07
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; jeffreyalaw<jeffreyalaw@gmail.com>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主 题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
You mean theadvector doesn't want the current RVV1.0 register overlap magic as follows ?
The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).
The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).
If yes, I suggest disable the overlap constraint using attribute, More details you can learn from
(set_attr "group_overlap"
juzhe.zhong@rivai.ai
发件人： joshua
发送时间： 2023-12-22 11:33
收件人： 钟居哲; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Jeff Law; Christoph Müllner; jinma; Cooper Qu
主题： 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our patchset more organized.
For 1) and 3), I will split out the patches soon and hope they will be merged quickly.
For 2), according to the differences between vector and xtheadvector, it can be classfied into 3 kinds.
First is renamed load/store, renamed narrowing integer right shift, renamed narrowing fixed-point clip, and etc. I think we can use ASM targethook to rewrite the whole string of the instructions, although it will still be a heavy work.
Second is no pseudo instruction like vneg/vfneg. We will add these pseudo instructions in binutils to make xtheadvector more compatible with vector.
Third is that destination vector register cannot overlap source vector register group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot come up with any better way than pattern copy. Do you have any suggestions?
Joshua
------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; Jeff Law<jeffreyalaw@gmail.com>; "Christoph Müllner"<christoph.muellner@vrull.eu>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主 题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out the better way to do that (Current this patch with copying patterns is not approach I like)
So, I hope you can break this big patch into 3 different series patches.
1. Support partial theadvector instructions which leverage directly from current RVV1.0 with simple adding "th." prefix.
2. Support totally different name theadvector instructions but share same patterns as RVV1.0 instructions.
3. Support new headvector instructions like vlib...etc.
I think 1 and 3 separate patches can be quickly merged after my more details reviewed and approved in the following patches you send like V4 ?.
For 2, it's a bit more complicate, but I think we can support like ARM and other targets, use ASM targethook to rewrite the whole string of the instructions.
For example, like strided load/store, you can know this instructions from attribute:
(set_attr "type" "vlds")
juzhe.zhong@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-20 20:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html
Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples,
and all the tests passed.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
---
gcc/common/config/riscv/riscv-common.cc | 23 +
gcc/config.gcc | 4 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 8 +-
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string.cc | 3 +
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 18 +-
.../riscv/riscv-vector-builtins-bases.h | 19 +
.../riscv/riscv-vector-builtins-shapes.cc | 149 +
.../riscv/riscv-vector-builtins-shapes.h | 3 +
.../riscv/riscv-vector-builtins-types.def | 120 +
gcc/config/riscv/riscv-vector-builtins.cc | 315 +-
gcc/config/riscv/riscv-vector-builtins.h | 5 +-
gcc/config/riscv/riscv-vector-switch.def | 150 +-
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/riscv_th_vector.h | 49 +
gcc/config/riscv/t-riscv | 16 +
.../riscv/thead-vector-builtins-functions.def | 659 ++++
gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++
gcc/config/riscv/thead-vector-builtins.h | 123 +
gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++
gcc/config/riscv/vector-iterators.md | 186 +-
gcc/config/riscv/vector.md | 44 +-
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
.../gcc.target/riscv/rvv/base/abi-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
.../gcc.target/riscv/rvv/xtheadvector.c | 13 +
.../riscv/rvv/xtheadvector/prefix.c | 12 +
.../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +
gcc/testsuite/lib/target-supports.exp | 12 +
39 files changed, 5931 insertions(+), 213 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins.h
create mode 100644 gcc/config/riscv/thead-vector.md
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
On 12/22/23 01:07, juzhe.zhong@rivai.ai wrote: > You mean theadvector doesn't want the current RVV1.0 register overlap > magic as follows ? > > * > > The destination EEW is smaller than the source EEW and the overlap > is in the lowest-numbered part of the source register group (e.g., > when LMUL=1, |vnsrl.wi v0, v0, 3| is legal, but a destination of > |v1| is not). > > * > > The destination EEW is greater than the source EEW, the source EMUL > is at least 1, and the overlap is in the highest-numbered part of > the destination register group (e.g., when LMUL=8, |vzext.vf4 v0, > v6| is legal, but a source of |v0|, |v2|, or |v4| is not). > > > If yes, I suggest disable the overlap constraint using attribute, More > details you can learn from Yea, if there's alternatives we want to allow for xthead, but not rvv or vice-versa, I would think the "enabled" attribute would be a reasonable option. Essentially it allows alternatives to be available or unavailable based on the subtarget. It sounds like this may be necessary because of differences in how overlap is handled across 0.7 vs 1.0. Jeff >
Hi Juzhe,
Sorry but I'm not quite familiar with the group_overlap framework. Could you take this pattern as an example to show how to disable an alternative in some target?
Joshua
------------------------------------------------------------------
发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
发送时间：2023年12月22日(星期五) 18:32
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; jeffreyalaw<jeffreyalaw@gmail.com>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主 题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Yeah.
(define_insn "@pred_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
(unspec:<VM>
[(minus:VI
(match_operand:VI 1 "register_operand" " 0, vr, vr")
(match_operand:VI 2 "register_operand" " vr, 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm, vm")
(unspec:<VM>
[(match_operand 4 "vector_length_operand" " rK, rK, rK")
(match_operand 5 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_VECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
(set (attr "avl_type_idx") (const_int 5))])
You should use an attribute to disable alternative 0 and alternative 1 constraint.
juzhe.zhong@rivai.ai
发件人： joshua <mailto:cooper.joshua@linux.alibaba.com >
发送时间： 2023-12-22 18:29
收件人： juzhe.zhong@rivai.ai <mailto:juzhe.zhong@rivai.ai >; gcc-patches <mailto:gcc-patches@gcc.gnu.org >
抄送： Jim Wilson <mailto:jim.wilson.gcc@gmail.com >; palmer <mailto:palmer@dabbelt.com >; andrew <mailto:andrew@sifive.com >; philipp.tomsich <mailto:philipp.tomsich@vrull.eu >; jeffreyalaw <mailto:jeffreyalaw@gmail.com >; christoph.muellner <mailto:christoph.muellner@vrull.eu >; jinma <mailto:jinma@linux.alibaba.com >; cooper.qu <mailto:cooper.qu@linux.alibaba.com >
主题： 回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
What xtheadvector needs to handle is just that destination vector register cannot overlap source vector register group for instructions like vmadc/vmsbc. That is not what group_overlap means. We nned to add "&" to the registers in the corresponding xtheadvector patterns while rvv 1.0 doesn't have this constraint.
(define_insn "@pred_th_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=&vr")
(unspec:<VM>
[(minus:VI
(match_operand:VI 1 "register_operand" " vr")
(match_operand:VI 2 "register_operand" " vr"))
(match_operand:<VM> 3 "register_operand" " vm")
(unspec:<VM>
[(match_operand 4 "vector_length_operand" " rK")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_XTHEADVECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
(set (attr "avl_type_idx") (const_int 5))])
Joshua
------------------------------------------------------------------
发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
发送时间：2023年12月22日(星期五) 16:07
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; jeffreyalaw<jeffreyalaw@gmail.com>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主 题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
You mean theadvector doesn't want the current RVV1.0 register overlap magic as follows ?
*
The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).
*
The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).
If yes, I suggest disable the overlap constraint using attribute, More details you can learn from
(set_attr "group_overlap"
juzhe.zhong@rivai.ai
发件人： joshua <mailto:cooper.joshua@linux.alibaba.com >
发送时间： 2023-12-22 11:33
收件人： 钟居哲 <mailto:juzhe.zhong@rivai.ai >; gcc-patches <mailto:gcc-patches@gcc.gnu.org >
抄送： jim.wilson.gcc <mailto:jim.wilson.gcc@gmail.com >; palmer <mailto:palmer@dabbelt.com >; andrew <mailto:andrew@sifive.com >; philipp.tomsich <mailto:philipp.tomsich@vrull.eu >; Jeff Law <mailto:jeffreyalaw@gmail.com >; Christoph Müllner <mailto:christoph.muellner@vrull.eu >; jinma <mailto:jinma@linux.alibaba.com >; Cooper Qu <mailto:cooper.qu@linux.alibaba.com >
主题： 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our patchset more organized.
For 1) and 3), I will split out the patches soon and hope they will be merged quickly.
For 2), according to the differences between vector and xtheadvector, it can be classfied into 3 kinds.
First is renamed load/store, renamed narrowing integer right shift, renamed narrowing fixed-point clip, and etc. I think we can use ASM targethook to rewrite the whole string of the instructions, although it will still be a heavy work.
Second is no pseudo instruction like vneg/vfneg. We will add these pseudo instructions in binutils to make xtheadvector more compatible with vector.
Third is that destination vector register cannot overlap source vector register group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot come up with any better way than pattern copy. Do you have any suggestions?
Joshua
------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; Jeff Law<jeffreyalaw@gmail.com>; "Christoph Müllner"<christoph.muellner@vrull.eu>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主 题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out the better way to do that (Current this patch with copying patterns is not approach I like)
So, I hope you can break this big patch into 3 different series patches.
1. Support partial theadvector instructions which leverage directly from current RVV1.0 with simple adding "th." prefix.
2. Support totally different name theadvector instructions but share same patterns as RVV1.0 instructions.
3. Support new headvector instructions like vlib...etc.
I think 1 and 3 separate patches can be quickly merged after my more details reviewed and approved in the following patches you send like V4 ?.
For 2, it's a bit more complicate, but I think we can support like ARM and other targets, use ASM targethook to rewrite the whole string of the instructions.
For example, like strided load/store, you can know this instructions from attribute:
(set_attr "type" "vlds")
juzhe.zhong@rivai.ai
From: Jun Sha (Joshua) <mailto:cooper.joshua@linux.alibaba.com >
Date: 2023-12-20 20:20
To: gcc-patches <mailto:gcc-patches@gcc.gnu.org >
CC: jim.wilson.gcc <mailto:jim.wilson.gcc@gmail.com >; palmer <mailto:palmer@dabbelt.com >; andrew <mailto:andrew@sifive.com >; philipp.tomsich <mailto:philipp.tomsich@vrull.eu >; jeffreyalaw <mailto:jeffreyalaw@gmail.com >; christoph.muellner <mailto:christoph.muellner@vrull.eu >; juzhe.zhong <mailto:juzhe.zhong@rivai.ai >; Jun Sha (Joshua) <mailto:cooper.joshua@linux.alibaba.com >; Jin Ma <mailto:jinma@linux.alibaba.com >; Xianmiao Qu <mailto:cooper.qu@linux.alibaba.com >
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/ <https://github.com/T-head-Semi/thead-extension-spec/ >
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html <https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html >
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html <https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html >
Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples <https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples >,
and all the tests passed.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
---
gcc/common/config/riscv/riscv-common.cc | 23 +
gcc/config.gcc | 4 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 8 +-
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string.cc | 3 +
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 18 +-
.../riscv/riscv-vector-builtins-bases.h | 19 +
.../riscv/riscv-vector-builtins-shapes.cc | 149 +
.../riscv/riscv-vector-builtins-shapes.h | 3 +
.../riscv/riscv-vector-builtins-types.def | 120 +
gcc/config/riscv/riscv-vector-builtins.cc | 315 +-
gcc/config/riscv/riscv-vector-builtins.h | 5 +-
gcc/config/riscv/riscv-vector-switch.def | 150 +-
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/riscv_th_vector.h | 49 +
gcc/config/riscv/t-riscv | 16 +
.../riscv/thead-vector-builtins-functions.def | 659 ++++
gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++
gcc/config/riscv/thead-vector-builtins.h | 123 +
gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++
gcc/config/riscv/vector-iterators.md | 186 +-
gcc/config/riscv/vector.md | 44 +-
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
.../gcc.target/riscv/rvv/base/abi-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
.../gcc.target/riscv/rvv/xtheadvector.c | 13 +
.../riscv/rvv/xtheadvector/prefix.c | 12 +
.../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +
gcc/testsuite/lib/target-supports.exp | 12 +
39 files changed, 5931 insertions(+), 213 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins.h
create mode 100644 gcc/config/riscv/thead-vector.md
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
I suggest you send the first patch which support theadvector with only adding "th.".
After it's done, then we can talk about it later.
juzhe.zhong@rivai.ai
发件人： joshua
发送时间： 2023-12-23 11:37
收件人： juzhe.zhong@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner
主题： 回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Sorry but I'm not quite familiar with the group_overlap framework. Could you take this pattern as an example to show how to disable an alternative in some target?
Joshua
------------------------------------------------------------------
发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
发送时间：2023年12月22日(星期五) 18:32
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; jeffreyalaw<jeffreyalaw@gmail.com>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主 题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Yeah.
(define_insn "@pred_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
(unspec:<VM>
[(minus:VI
(match_operand:VI 1 "register_operand" " 0, vr, vr")
(match_operand:VI 2 "register_operand" " vr, 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm, vm")
(unspec:<VM>
[(match_operand 4 "vector_length_operand" " rK, rK, rK")
(match_operand 5 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_VECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
(set (attr "avl_type_idx") (const_int 5))])
You should use an attribute to disable alternative 0 and alternative 1 constraint.
juzhe.zhong@rivai.ai
发件人： joshua
发送时间： 2023-12-22 18:29
收件人： juzhe.zhong@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu
主题： 回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
What xtheadvector needs to handle is just that destination vector register cannot overlap source vector register group for instructions like vmadc/vmsbc. That is not what group_overlap means. We nned to add "&" to the registers in the corresponding xtheadvector patterns while rvv 1.0 doesn't have this constraint.
(define_insn "@pred_th_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=&vr")
(unspec:<VM>
[(minus:VI
(match_operand:VI 1 "register_operand" " vr")
(match_operand:VI 2 "register_operand" " vr"))
(match_operand:<VM> 3 "register_operand" " vm")
(unspec:<VM>
[(match_operand 4 "vector_length_operand" " rK")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_XTHEADVECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
(set (attr "avl_type_idx") (const_int 5))])
Joshua
------------------------------------------------------------------
发件人：juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
发送时间：2023年12月22日(星期五) 16:07
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送：Jim Wilson<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; jeffreyalaw<jeffreyalaw@gmail.com>; "christoph.muellner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; "cooper.qu"<cooper.qu@linux.alibaba.com>
主 题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
You mean theadvector doesn't want the current RVV1.0 register overlap magic as follows ?
The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).
The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).
If yes, I suggest disable the overlap constraint using attribute, More details you can learn from
(set_attr "group_overlap"
juzhe.zhong@rivai.ai
发件人： joshua
发送时间： 2023-12-22 11:33
收件人： 钟居哲; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Jeff Law; Christoph Müllner; jinma; Cooper Qu
主题： 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our patchset more organized.
For 1) and 3), I will split out the patches soon and hope they will be merged quickly.
For 2), according to the differences between vector and xtheadvector, it can be classfied into 3 kinds.
First is renamed load/store, renamed narrowing integer right shift, renamed narrowing fixed-point clip, and etc. I think we can use ASM targethook to rewrite the whole string of the instructions, although it will still be a heavy work.
Second is no pseudo instruction like vneg/vfneg. We will add these pseudo instructions in binutils to make xtheadvector more compatible with vector.
Third is that destination vector register cannot overlap source vector register group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot come up with any better way than pattern copy. Do you have any suggestions?
Joshua
------------------------------------------------------------------
发件人：钟居哲 <juzhe.zhong@rivai.ai>
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送："jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; Jeff Law<jeffreyalaw@gmail.com>; "Christoph Müllner"<christoph.muellner@vrull.eu>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主 题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out the better way to do that (Current this patch with copying patterns is not approach I like)
So, I hope you can break this big patch into 3 different series patches.
1. Support partial theadvector instructions which leverage directly from current RVV1.0 with simple adding "th." prefix.
2. Support totally different name theadvector instructions but share same patterns as RVV1.0 instructions.
3. Support new headvector instructions like vlib...etc.
I think 1 and 3 separate patches can be quickly merged after my more details reviewed and approved in the following patches you send like V4 ?.
For 2, it's a bit more complicate, but I think we can support like ARM and other targets, use ASM targethook to rewrite the whole string of the instructions.
For example, like strided load/store, you can know this instructions from attribute:
(set_attr "type" "vlds")
juzhe.zhong@rivai.ai
From: Jun Sha (Joshua)
Date: 2023-12-20 20:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html
Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples,
and all the tests passed.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
---
gcc/common/config/riscv/riscv-common.cc | 23 +
gcc/config.gcc | 4 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 8 +-
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string.cc | 3 +
gcc/config/riscv/riscv-v.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.cc | 18 +-
.../riscv/riscv-vector-builtins-bases.h | 19 +
.../riscv/riscv-vector-builtins-shapes.cc | 149 +
.../riscv/riscv-vector-builtins-shapes.h | 3 +
.../riscv/riscv-vector-builtins-types.def | 120 +
gcc/config/riscv/riscv-vector-builtins.cc | 315 +-
gcc/config/riscv/riscv-vector-builtins.h | 5 +-
gcc/config/riscv/riscv-vector-switch.def | 150 +-
gcc/config/riscv/riscv.cc | 46 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.opt | 2 +
gcc/config/riscv/riscv_th_vector.h | 49 +
gcc/config/riscv/t-riscv | 16 +
.../riscv/thead-vector-builtins-functions.def | 659 ++++
gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++
gcc/config/riscv/thead-vector-builtins.h | 123 +
gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++
gcc/config/riscv/vector-iterators.md | 186 +-
gcc/config/riscv/vector.md | 44 +-
.../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
.../gcc.target/riscv/rvv/base/abi-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
.../gcc.target/riscv/rvv/xtheadvector.c | 13 +
.../riscv/rvv/xtheadvector/prefix.c | 12 +
.../riscv/rvv/xtheadvector/vlb-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 +
.../riscv/rvv/xtheadvector/vlh-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 +
.../riscv/rvv/xtheadvector/vlw-vsw.c | 68 +
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 +
gcc/testsuite/lib/target-supports.exp | 12 +
39 files changed, 5931 insertions(+), 213 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins.h
create mode 100644 gcc/config/riscv/thead-vector.md
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c