From patchwork Sat Aug 12 02:30:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 1820479 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RN4QR6lcCz1yfN for ; Sat, 12 Aug 2023 12:30:37 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 57F88385700C for ; Sat, 12 Aug 2023 02:30:35 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id 72CD23858409 for ; Sat, 12 Aug 2023 02:30:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 72CD23858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1691807407tk76ubnh Received: from server1.localdomain ( [58.60.1.10]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 12 Aug 2023 10:30:06 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: CR3LFp2JE4l4/wD5NA/izSaZfImCcs2pUA/83rpu56VrpbkvnXkE7tNsPUnhw 3y4WUYF07uTENWv3XmgxN3kmDuy1BxfwdrcJjCCkr7QTjqtfy120YtDKT+fAR3UhBX95Cjf hNtRo0nh27fnGmjCTrGVznmNeSR2WOMSBcpJUmGbjxEyhwYIuj+oR9q2nSoRkviNX0X8W1J 9o122DJs72FFnG+ShBwzw/tP4NqazgVzkIccLsbONRCz0/UhC4bjNQ4UCWfjkKXcKDQJj+I HbsjJsjnWkhTtQKhV5gT1H0QUoamK0yjUXGXI0XhMFQ7oljyozXcUnJ6kzPQ8nbI1taYgjj R1vvup+rlSj+a7EhrgLTYOY2i8H081I5r384GuABiNtfsprievHVAefMbyFnQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17100482953792397639 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add TAREGT_VECTOR check into VLS modes Date: Sat, 12 Aug 2023 10:30:02 +0800 Message-Id: <20230812023002.238780-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994 This is caused VLS modes incorrect codes int register allocation. The original case trigger the ICE is fortran code but I can reproduce with a C code. PR target/110994 gcc/ChangeLog: * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test. --- gcc/config/riscv/riscv-opts.h | 3 ++- .../gcc.target/riscv/rvv/autovec/vls/pr110994.c | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index d6d785d0075..aeea805b342 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -300,6 +300,7 @@ enum riscv_entity /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode is the highest priority choice and should not conflict with VLS modes. */ -#define TARGET_VECTOR_VLS (riscv_autovec_preference == RVV_SCALABLE) +#define TARGET_VECTOR_VLS \ + (TARGET_VECTOR && riscv_autovec_preference == RVV_SCALABLE) #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c new file mode 100644 index 00000000000..fcacc78b7a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */ + +#include "def.h" + +void foo (int8_t *in, int8_t *out) +{ + v4qi v = *(v4qi*)in; + *(v4qi*)out = v; +}