diff mbox series

[v2,05/14] LoongArch: Fix 64-bit move for loongarch32 target

Message ID 20230809115325.3716347-6-c@jia.je
State New
Headers show
Series LoongArch: Add loongarch32 and ilp32 abi | expand

Commit Message

Jiajie Chen Aug. 9, 2023, 11:46 a.m. UTC 
Bring back 64-bit move splitting for loongarch32. The code was removed
in commit 16fc26d4e7a (`LoongArch: Support split symbol.`) for unknown
reason.

gcc/ChangeLog:

	* config/loongarch/loongarch.md: Handle move splitting for
	64-bit operands.
---
 gcc/config/loongarch/loongarch.md | 10 ++++++++++
 1 file changed, 10 insertions(+)
diff mbox series

Patch

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 93d8bf5bcca..9eb6bb75c35 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1965,6 +1965,16 @@ 
   [(set_attr "move_type" "move,load,store")
    (set_attr "mode" "DF")])
 
+(define_split
+  [(set (match_operand:MOVE64 0 "nonimmediate_operand")
+       (match_operand:MOVE64 1 "move_operand"))]
+  "reload_completed && loongarch_split_move_p (operands[0], operands[1])"
+  [(const_int 0)]
+{
+  loongarch_split_move (operands[0], operands[1], curr_insn);
+  DONE;
+})
+
 ;; Emit a doubleword move in which exactly one of the operands is
 ;; a floating-point register.  We can't just emit two normal moves
 ;; because of the constraints imposed by the FPU register model;