From patchwork Wed Aug 9 11:46:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819272 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=Q3C/U78L; dkim-atps=neutral Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT5H49mHz1yfB for ; Wed, 9 Aug 2023 21:55:15 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CD3883865C1D for ; Wed, 9 Aug 2023 11:55:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CD3883865C1D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582112; bh=syLQcoV0mILoIS3zd83SZgqXrLxzbvXSjY0P4fpMT2w=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Q3C/U78L6WYcvDVHfuYtVuoItop7RM9aD5wd00BD+34lqn94jOk0Of8/zxHCfsHBB nPU6SbJpfEBoTQpGP1qpWXwyoo6RleDDF71qd/HbhegZTPEEBlAf/AQo2NdR8pVbrI H5uO7+MhK4YwSSBFIQNlZFtVK5n2WtCNorf1SqwE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 367CB3857B8E for ; Wed, 9 Aug 2023 11:53:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 367CB3857B8E Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 1E6314402F; Wed, 9 Aug 2023 11:53:48 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 01/14] LoongArch: Introduce loongarch32 target Date: Wed, 9 Aug 2023 19:46:08 +0800 Message-ID: <20230809115325.3716347-2-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Introduce loongarch32 target and ilp32 abi variants. The ilp32d abi variant is selected as the default abi of loongarch32 target. Currently, ilp32 abi can only be used for loongarch32, but in the future, it might be possible to use ilp32 abi for loongarch64. contrib/ChangeLog: * config-list.mk: Add loongarch32-linux-gnu*. gcc/ChangeLog: * config.gcc: Add target triple loongarch32-*-*-* and corresponding abi ilp32f, ilp32d and ilp32s. * config/loongarch/genopts/loongarch-strings: Add strings for loongarch32 and ilp32 abi variants. * config/loongarch/genopts/loongarch.opt.in: Add -march=loongarch32 and -mabi=ilp32d/ilp32f/ilp32s. * config/loongarch/gnu-user.h: Add ilp32 abi variants to spec. * config/loongarch/linux.h: Add ABI_LIBDIR for ilp32 abi variants. * config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins): Add builtin definitions for loongarch32 target. * config/loongarch/loongarch-def.c: Add loongarch32 and ilp32 definitions. * config/loongarch/loongarch-def.h: Add loongarch32 and ilp32 definitions. * config/loongarch/loongarch-driver.h: Add ilp32 abi variants to spec. * config/loongarch/loongarch-opts.cc: Handle ilp32 abi variants. * config/loongarch/loongarch-opts.h: Add loongarch32 case to macros. * config/loongarch/loongarch-str.h: Add loongarch32 and ilp32 strings. * config/loongarch/loongarch.cc: Disable -fpcc-struct-return for ilp32. * config/loongarch/loongarch.opt: Add -march=loongarch32 and -mabi=ilp32d/ilp32f/ilp32s. * config/loongarch/t-linux: Add ilp32 abi variants to multilib. --- contrib/config-list.mk | 1 + gcc/config.gcc | 61 ++++++++++++++++--- .../loongarch/genopts/loongarch-strings | 5 ++ gcc/config/loongarch/genopts/loongarch.opt.in | 12 ++++ gcc/config/loongarch/gnu-user.h | 3 + gcc/config/loongarch/linux.h | 8 ++- gcc/config/loongarch/loongarch-c.cc | 12 ++++ gcc/config/loongarch/loongarch-def.c | 33 ++++++++++ gcc/config/loongarch/loongarch-def.h | 25 +++++--- gcc/config/loongarch/loongarch-driver.h | 4 ++ gcc/config/loongarch/loongarch-opts.cc | 22 ++++++- gcc/config/loongarch/loongarch-opts.h | 20 ++++-- gcc/config/loongarch/loongarch-str.h | 5 ++ gcc/config/loongarch/loongarch.cc | 2 +- gcc/config/loongarch/loongarch.opt | 12 ++++ gcc/config/loongarch/t-linux | 16 ++++- 16 files changed, 210 insertions(+), 31 deletions(-) diff --git a/contrib/config-list.mk b/contrib/config-list.mk index e570b13c71b..3c00ce5410a 100644 --- a/contrib/config-list.mk +++ b/contrib/config-list.mk @@ -57,6 +57,7 @@ LIST = aarch64-elf aarch64-freebsd13 aarch64-linux-gnu aarch64-rtems \ i686-cygwinOPT-enable-threads=yes i686-mingw32crt ia64-elf \ ia64-linux ia64-hpux ia64-hp-vms iq2000-elf lm32-elf \ lm32-rtems lm32-uclinux \ + loongarch32-linux-gnuf64 loongarch32-linux-gnuf32 loongarch32-linux-gnusf \ loongarch64-linux-gnuf64 loongarch64-linux-gnuf32 loongarch64-linux-gnusf \ m32c-elf m32r-elf m32rle-elf \ m68k-elf m68k-netbsdelf \ diff --git a/gcc/config.gcc b/gcc/config.gcc index 415e0e1ebc5..45e69b24b44 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4901,10 +4901,24 @@ case "${target}" in arch_pattern arch_default \ fpu_pattern fpu_default \ tune_pattern tune_default \ - triplet_os triplet_abi + triplet_os triplet_abi \ + triplet_cpu # Infer ABI from the triplet. case ${target} in + loongarch32-*-*-*f64) + abi_pattern="ilp32d" + ;; + loongarch32-*-*-*f32) + abi_pattern="ilp32f" + ;; + loongarch32-*-*-*sf) + abi_pattern="ilp32s" + ;; + loongarch32-*-*-*) + abi_pattern="ilp32[dfs]" + abi_default="ilp32d" + ;; loongarch64-*-*-*f64) abi_pattern="lp64d" ;; @@ -4939,7 +4953,7 @@ case "${target}" in # Perform initial sanity checks on --with-* options. case ${with_arch} in - "" | loongarch64 | la464) ;; # OK, append here. + "" | loongarch32 | loongarch64 | la464) ;; # OK, append here. native) if test x${host} != x${target}; then echo "--with-arch=native is illegal for cross-compiler." 1>&2 @@ -4958,7 +4972,7 @@ case "${target}" in esac case ${with_abi} in - "" | lp64d | lp64f | lp64s) ;; # OK, append here. + "" | ilp32d | ilp32f | ilp32s | lp64d | lp64f | lp64s) ;; # OK, append here. *) echo "Unsupported ABI given in --with-abi=$with_abi" 1>&2 exit 1 @@ -5007,12 +5021,21 @@ case "${target}" in ;; esac + case ${target} in + loongarch32-*-*-*) + triplet_cpu="loongarch32" + ;; + loongarch64-*-*-*) + triplet_cpu="loongarch64" + ;; + esac + case ${with_abi} in - "lp64d") triplet_abi="";; - "lp64f") triplet_abi="f32";; - "lp64s") triplet_abi="sf";; + "ilp32d" | "lp64d") triplet_abi="";; + "ilp32f" | "lp64f") triplet_abi="f32";; + "ilp32s" | "lp64s") triplet_abi="sf";; esac - la_canonical_triplet="loongarch64-${triplet_os}${triplet_abi}" + la_canonical_triplet="${triplet_cpu}-${triplet_os}${triplet_abi}" # Set default value for with_abiext (internal) case ${with_abiext} in @@ -5038,6 +5061,12 @@ case "${target}" in # Infer ISA-related default options from the ABI: pass 1 case ${with_abi}/${with_abiext} in + ilp32*/base) + # architectures that support ilp32* ABI + arch_pattern="native|loongarch32" + # default architecture for ilp32* ABI + arch_default="loongarch32" + ;; lp64*/base) # architectures that support lp64* ABI arch_pattern="native|loongarch64|la464" @@ -5052,14 +5081,14 @@ case "${target}" in # Infer ISA-related default options from the ABI: pass 2 case ${with_abi}/${with_abiext} in - lp64d/base) + ilp32d/base | lp64d/base) fpu_pattern="64" ;; - lp64f/base) + ilp32f/base | lp64f/base) fpu_pattern="32|64" fpu_default="32" ;; - lp64s/base) + ilp32s/base | lp64s/base) fpu_pattern="none|32|64" fpu_default="none" ;; @@ -5118,6 +5147,10 @@ case "${target}" in tune_pattern="*" tune_default="native" ;; + loongarch32) + tune_pattern="loongarch32" + tune_default="loongarch32" + ;; loongarch64) tune_pattern="loongarch64|la464" tune_default="la464" @@ -5187,6 +5220,9 @@ case "${target}" in 1) # Component 1: Base ABI type case ${component} in + ilp32d) elem_tmp="ABI_BASE_ILP32D,";; + ilp32f) elem_tmp="ABI_BASE_ILP32F,";; + ilp32s) elem_tmp="ABI_BASE_ILP32S,";; lp64d) elem_tmp="ABI_BASE_LP64D,";; lp64f) elem_tmp="ABI_BASE_LP64F,";; lp64s) elem_tmp="ABI_BASE_LP64S,";; @@ -5741,17 +5777,22 @@ case ${target} in # See macro definitions from loongarch-opts.h and loongarch-cpu.h. case ${with_arch} in native) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_NATIVE" ;; + loongarch32) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LOONGARCH32" ;; la464) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LA464" ;; loongarch64) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LOONGARCH64" ;; esac case ${with_tune} in native) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_NATIVE" ;; + loongarch32) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LOONGARCH32" ;; la464) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LA464" ;; loongarch64) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LOONGARCH64" ;; esac case ${with_abi} in + ilp32d) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32D" ;; + ilp32f) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32F" ;; + ilp32s) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32S" ;; lp64d) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64D" ;; lp64f) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64F" ;; lp64s) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64S" ;; diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index a40998ead97..1e20b70dde2 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -23,10 +23,12 @@ OPTSTR_ARCH arch OPTSTR_TUNE tune STR_CPU_NATIVE native +STR_CPU_LOONGARCH32 loongarch32 STR_CPU_LOONGARCH64 loongarch64 STR_CPU_LA464 la464 # Base architecture +STR_ISA_BASE_LA32V100 la32 STR_ISA_BASE_LA64V100 la64 # -mfpu @@ -42,6 +44,9 @@ OPTSTR_DOUBLE_FLOAT double-float # -mabi= OPTSTR_ABI_BASE abi +STR_ABI_BASE_ILP32D ilp32d +STR_ABI_BASE_ILP32F ilp32f +STR_ABI_BASE_ILP32S ilp32s STR_ABI_BASE_LP64D lp64d STR_ABI_BASE_LP64F lp64f STR_ABI_BASE_LP64S lp64s diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 4b9b4ac273e..47f77345890 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -85,6 +85,9 @@ LoongArch CPU types: EnumValue Enum(cpu_type) String(@@STR_CPU_NATIVE@@) Value(CPU_NATIVE) +EnumValue +Enum(cpu_type) String(@@STR_CPU_LOONGARCH32@@) Value(CPU_LOONGARCH32) + EnumValue Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64) @@ -108,6 +111,15 @@ Enum Name(abi_base) Type(int) Base ABI types for LoongArch: +EnumValue +Enum(abi_base) String(@@STR_ABI_BASE_ILP32D@@) Value(ABI_BASE_ILP32D) + +EnumValue +Enum(abi_base) String(@@STR_ABI_BASE_ILP32F@@) Value(ABI_BASE_ILP32F) + +EnumValue +Enum(abi_base) String(@@STR_ABI_BASE_ILP32S@@) Value(ABI_BASE_ILP32S) + EnumValue Enum(abi_base) String(@@STR_ABI_BASE_LP64D@@) Value(ABI_BASE_LP64D) diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h index fa1a5211419..bf6d3a4fe98 100644 --- a/gcc/config/loongarch/gnu-user.h +++ b/gcc/config/loongarch/gnu-user.h @@ -34,6 +34,9 @@ along with GCC; see the file COPYING3. If not see "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1" #define MUSL_ABI_SPEC \ + "%{mabi=ilp32d:-ilp32d}" \ + "%{mabi=ilp32f:-ilp32f}" \ + "%{mabi=ilp32s:-ilp32s}" \ "%{mabi=lp64d:-lp64d}" \ "%{mabi=lp64f:-lp64f}" \ "%{mabi=lp64s:-lp64s}" diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h index 9059d244190..45aa3531cd3 100644 --- a/gcc/config/loongarch/linux.h +++ b/gcc/config/loongarch/linux.h @@ -23,7 +23,13 @@ along with GCC; see the file COPYING3. If not see #if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH) - #if DEFAULT_ABI_BASE == ABI_BASE_LP64D + #if DEFAULT_ABI_BASE == ABI_BASE_ILP32D + #define ABI_LIBDIR "lib32" + #elif DEFAULT_ABI_BASE == ABI_BASE_ILP32F + #define ABI_LIBDIR "lib32/f32" + #elif DEFAULT_ABI_BASE == ABI_BASE_ILP32S + #define ABI_LIBDIR "lib32/sf" + #elif DEFAULT_ABI_BASE == ABI_BASE_LP64D #define ABI_LIBDIR "lib64" #elif DEFAULT_ABI_BASE == ABI_BASE_LP64F #define ABI_LIBDIR "lib64/f32" diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc index 67911b78f28..e3783a325d7 100644 --- a/gcc/config/loongarch/loongarch-c.cc +++ b/gcc/config/loongarch/loongarch-c.cc @@ -65,12 +65,24 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile) LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_TUNE", LARCH_ACTUAL_TUNE); /* Base architecture / ABI. */ + if (TARGET_32BIT) + { + builtin_define ("__loongarch_grlen=32"); + builtin_define ("__loongarch32"); + } if (TARGET_64BIT) { builtin_define ("__loongarch_grlen=64"); builtin_define ("__loongarch64"); } + if (TARGET_ABI_ILP32) + { + builtin_define ("_ABILP32=3"); + builtin_define ("_LOONGARCH_SIM=_ABILP32"); + builtin_define ("__loongarch_ilp32"); + } + if (TARGET_ABI_LP64) { builtin_define ("_ABILP64=3"); diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c index 6729c857f7c..5ae8bd24c9f 100644 --- a/gcc/config/loongarch/loongarch-def.c +++ b/gcc/config/loongarch/loongarch-def.c @@ -40,12 +40,17 @@ along with GCC; see the file COPYING3. If not see const char* loongarch_cpu_strings[N_TUNE_TYPES] = { [CPU_NATIVE] = STR_CPU_NATIVE, + [CPU_LOONGARCH32] = STR_CPU_LOONGARCH32, [CPU_LOONGARCH64] = STR_CPU_LOONGARCH64, [CPU_LA464] = STR_CPU_LA464, }; struct loongarch_isa loongarch_cpu_default_isa[N_ARCH_TYPES] = { + [CPU_LOONGARCH32] = { + .base = ISA_BASE_LA32V100, + .fpu = ISA_EXT_FPU32, + }, [CPU_LOONGARCH64] = { .base = ISA_BASE_LA64V100, .fpu = ISA_EXT_FPU64, @@ -58,6 +63,12 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = { struct loongarch_cache loongarch_cpu_cache[N_TUNE_TYPES] = { + [CPU_LOONGARCH32] = { + .l1d_line_size = 64, + .l1d_size = 64, + .l2d_size = 256, + .simultaneous_prefetches = 4, + }, [CPU_LOONGARCH64] = { .l1d_line_size = 64, .l1d_size = 64, @@ -74,6 +85,10 @@ loongarch_cpu_cache[N_TUNE_TYPES] = { struct loongarch_align loongarch_cpu_align[N_TUNE_TYPES] = { + [CPU_LOONGARCH32] = { + .function = "32", + .label = "16", + }, [CPU_LOONGARCH64] = { .function = "32", .label = "16", @@ -94,6 +109,9 @@ loongarch_cpu_rtx_cost_data[N_TUNE_TYPES] = { [CPU_NATIVE] = { DEFAULT_COSTS }, + [CPU_LOONGARCH32] = { + DEFAULT_COSTS + }, [CPU_LOONGARCH64] = { DEFAULT_COSTS }, @@ -121,6 +139,7 @@ loongarch_rtx_cost_optimize_size = { int loongarch_cpu_issue_rate[N_TUNE_TYPES] = { [CPU_NATIVE] = 4, + [CPU_LOONGARCH32] = 4, [CPU_LOONGARCH64] = 4, [CPU_LA464] = 4, }; @@ -128,6 +147,7 @@ loongarch_cpu_issue_rate[N_TUNE_TYPES] = { int loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = { [CPU_NATIVE] = 4, + [CPU_LOONGARCH32] = 4, [CPU_LOONGARCH64] = 4, [CPU_LA464] = 4, }; @@ -139,6 +159,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = { const char* loongarch_isa_base_strings[N_ISA_BASE_TYPES] = { + [ISA_BASE_LA32V100] = STR_ISA_BASE_LA32V100, [ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100, }; @@ -151,6 +172,9 @@ loongarch_isa_ext_strings[N_ISA_EXT_TYPES] = { const char* loongarch_abi_base_strings[N_ABI_BASE_TYPES] = { + [ABI_BASE_ILP32D] = STR_ABI_BASE_ILP32D, + [ABI_BASE_ILP32F] = STR_ABI_BASE_ILP32F, + [ABI_BASE_ILP32S] = STR_ABI_BASE_ILP32S, [ABI_BASE_LP64D] = STR_ABI_BASE_LP64D, [ABI_BASE_LP64F] = STR_ABI_BASE_LP64F, [ABI_BASE_LP64S] = STR_ABI_BASE_LP64S, @@ -182,6 +206,15 @@ loongarch_switch_strings[] = { /* ABI-related definitions. */ const struct loongarch_isa abi_minimal_isa[N_ABI_BASE_TYPES][N_ABI_EXT_TYPES] = { + [ABI_BASE_ILP32D] = { + [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_FPU64}, + }, + [ABI_BASE_ILP32F] = { + [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_FPU32}, + }, + [ABI_BASE_ILP32S] = { + [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_NOFPU}, + }, [ABI_BASE_LP64D] = { [ABI_EXT_BASE] = {.base = ISA_BASE_LA64V100, .fpu = ISA_EXT_FPU64}, }, diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index fb8bb88eb52..6c4b9fa3385 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -54,8 +54,9 @@ extern "C" { /* enum isa_base */ extern const char* loongarch_isa_base_strings[]; -#define ISA_BASE_LA64V100 0 -#define N_ISA_BASE_TYPES 1 +#define ISA_BASE_LA32V100 0 +#define ISA_BASE_LA64V100 1 +#define N_ISA_BASE_TYPES 2 /* enum isa_ext_* */ extern const char* loongarch_isa_ext_strings[]; @@ -67,10 +68,13 @@ extern const char* loongarch_isa_ext_strings[]; /* enum abi_base */ extern const char* loongarch_abi_base_strings[]; -#define ABI_BASE_LP64D 0 -#define ABI_BASE_LP64F 1 -#define ABI_BASE_LP64S 2 -#define N_ABI_BASE_TYPES 3 +#define ABI_BASE_ILP32D 0 +#define ABI_BASE_ILP32F 1 +#define ABI_BASE_ILP32S 2 +#define ABI_BASE_LP64D 3 +#define ABI_BASE_LP64F 4 +#define ABI_BASE_LP64S 5 +#define N_ABI_BASE_TYPES 6 /* enum abi_ext */ extern const char* loongarch_abi_ext_strings[]; @@ -132,10 +136,11 @@ struct loongarch_target /* CPU properties. */ /* index */ #define CPU_NATIVE 0 -#define CPU_LOONGARCH64 1 -#define CPU_LA464 2 -#define N_ARCH_TYPES 3 -#define N_TUNE_TYPES 3 +#define CPU_LOONGARCH32 1 +#define CPU_LOONGARCH64 2 +#define CPU_LA464 3 +#define N_ARCH_TYPES 4 +#define N_TUNE_TYPES 4 /* parallel tables. */ extern const char* loongarch_cpu_strings[]; diff --git a/gcc/config/loongarch/loongarch-driver.h b/gcc/config/loongarch/loongarch-driver.h index ba8817a4621..0a22acab803 100644 --- a/gcc/config/loongarch/loongarch-driver.h +++ b/gcc/config/loongarch/loongarch-driver.h @@ -58,9 +58,13 @@ driver_get_normalized_m_opts (int argc, const char **argv); /* ABI spec strings. */ #define ABI_GRLEN_SPEC \ + "%{mabi=ilp32*:32}" \ "%{mabi=lp64*:64}" \ #define ABI_SPEC \ + "%{mabi=ilp32d:ilp32d}" \ + "%{mabi=ilp32f:ilp32f}" \ + "%{mabi=ilp32s:ilp32s}" \ "%{mabi=lp64d:lp64d}" \ "%{mabi=lp64f:lp64f}" \ "%{mabi=lp64s:lp64s}" \ diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index a52e25236ea..9fc0bbbcb6e 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -36,6 +36,9 @@ struct loongarch_target la_target; #define ABI_COUNT (sizeof(abi_priority_list)/sizeof(struct loongarch_abi)) static const struct loongarch_abi abi_priority_list[] = { + {ABI_BASE_ILP32D, ABI_EXT_BASE}, + {ABI_BASE_ILP32F, ABI_EXT_BASE}, + {ABI_BASE_ILP32S, ABI_EXT_BASE}, {ABI_BASE_LP64D, ABI_EXT_BASE}, {ABI_BASE_LP64F, ABI_EXT_BASE}, {ABI_BASE_LP64S, ABI_EXT_BASE}, @@ -410,17 +413,23 @@ isa_default_abi (const struct loongarch_isa *isa) switch (isa->fpu) { case ISA_EXT_FPU64: - if (isa->base == ISA_BASE_LA64V100) + if (isa->base == ISA_BASE_LA32V100) + abi.base = ABI_BASE_ILP32D; + else if (isa->base == ISA_BASE_LA64V100) abi.base = ABI_BASE_LP64D; break; case ISA_EXT_FPU32: - if (isa->base == ISA_BASE_LA64V100) + if (isa->base == ISA_BASE_LA32V100) + abi.base = ABI_BASE_ILP32F; + else if (isa->base == ISA_BASE_LA64V100) abi.base = ABI_BASE_LP64F; break; case ISA_EXT_NOFPU: - if (isa->base == ISA_BASE_LA64V100) + if (isa->base == ISA_BASE_LA32V100) + abi.base = ABI_BASE_ILP32S; + else if (isa->base == ISA_BASE_LA64V100) abi.base = ABI_BASE_LP64S; break; @@ -439,6 +448,8 @@ isa_base_compat_p (const struct loongarch_isa *set1, { switch (set2->base) { + case ISA_BASE_LA32V100: + return (set1->base == ISA_BASE_LA32V100); case ISA_BASE_LA64V100: return (set1->base == ISA_BASE_LA64V100); @@ -487,6 +498,11 @@ abi_default_cpu_arch (struct loongarch_abi abi) { switch (abi.base) { + case ABI_BASE_ILP32D: + case ABI_BASE_ILP32F: + case ABI_BASE_ILP32S: + if (abi.ext == ABI_EXT_BASE) + return CPU_LOONGARCH32; case ABI_BASE_LP64D: case ABI_BASE_LP64F: case ABI_BASE_LP64S: diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index b1ff54426e4..c8794dff0ad 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -51,15 +51,25 @@ loongarch_config_target (struct loongarch_target *target, #define TARGET_CMODEL_EXTREME (la_target.cmodel == CMODEL_EXTREME) #define TARGET_HARD_FLOAT (la_target.isa.fpu != ISA_EXT_NOFPU) -#define TARGET_HARD_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D \ +#define TARGET_HARD_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32D \ + || la_target.abi.base == ABI_BASE_ILP32F \ + || la_target.abi.base == ABI_BASE_LP64D \ || la_target.abi.base == ABI_BASE_LP64F) #define TARGET_SOFT_FLOAT (la_target.isa.fpu == ISA_EXT_NOFPU) -#define TARGET_SOFT_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64S) +#define TARGET_SOFT_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32S \ + || la_target.abi.base == ABI_BASE_LP64S) #define TARGET_SINGLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU32) -#define TARGET_SINGLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64F) +#define TARGET_SINGLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32F \ + || la_target.abi.base == ABI_BASE_LP64F) #define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64) -#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D) +#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32D \ + || la_target.abi.base == ABI_BASE_LP64D) + +#define TARGET_32BIT (la_target.isa.base == ISA_BASE_LA32V100) +#define TARGET_ABI_ILP32 (la_target.abi.base == ABI_BASE_ILP32D \ + || la_target.abi.base == ABI_BASE_ILP32F \ + || la_target.abi.base == ABI_BASE_ILP32S) #define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100) #define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \ @@ -78,9 +88,11 @@ loongarch_config_target (struct loongarch_target *target, ? (la_target.cpu_native) : (CPU_NATIVE)) \ : (la_target.cpu_tune)) +#define TARGET_ARCH_LOONGARCH32 (LARCH_ACTUAL_ARCH == CPU_LOONGARCH32) #define TARGET_ARCH_LOONGARCH64 (LARCH_ACTUAL_ARCH == CPU_LOONGARCH64) #define TARGET_ARCH_LA464 (LARCH_ACTUAL_ARCH == CPU_LA464) +#define TARGET_TUNE_LOONGARCH32 (LARCH_ACTUAL_TUNE == CPU_LOONGARCH32) #define TARGET_TUNE_LOONGARCH64 (LARCH_ACTUAL_TUNE == CPU_LOONGARCH64) #define TARGET_TUNE_LA464 (LARCH_ACTUAL_TUNE == CPU_LA464) diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index af2e82a321f..60588da45e2 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -27,9 +27,11 @@ along with GCC; see the file COPYING3. If not see #define OPTSTR_TUNE "tune" #define STR_CPU_NATIVE "native" +#define STR_CPU_LOONGARCH32 "loongarch32" #define STR_CPU_LOONGARCH64 "loongarch64" #define STR_CPU_LA464 "la464" +#define STR_ISA_BASE_LA32V100 "la32" #define STR_ISA_BASE_LA64V100 "la64" #define OPTSTR_ISA_EXT_FPU "fpu" @@ -43,6 +45,9 @@ along with GCC; see the file COPYING3. If not see #define OPTSTR_DOUBLE_FLOAT "double-float" #define OPTSTR_ABI_BASE "abi" +#define STR_ABI_BASE_ILP32D "ilp32d" +#define STR_ABI_BASE_ILP32F "ilp32f" +#define STR_ABI_BASE_ILP32S "ilp32s" #define STR_ABI_BASE_LP64D "lp64d" #define STR_ABI_BASE_LP64F "lp64f" #define STR_ABI_BASE_LP64S "lp64s" diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 86d58784113..c980de98758 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -6209,7 +6209,7 @@ loongarch_option_override_internal (struct gcc_options *opts) la_opt_cpu_arch, la_opt_cpu_tune, la_opt_fpu, la_opt_abi_base, la_opt_abi_ext, la_opt_cmodel, 0); - if (TARGET_ABI_LP64) + if (TARGET_ABI_LP64 || TARGET_ABI_ILP32) flag_pcc_struct_return = 0; /* Decide which rtx_costs structure to use. */ diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 68018ade73f..2cd36c5e8fa 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -92,6 +92,9 @@ LoongArch CPU types: EnumValue Enum(cpu_type) String(native) Value(CPU_NATIVE) +EnumValue +Enum(cpu_type) String(loongarch32) Value(CPU_LOONGARCH32) + EnumValue Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64) @@ -115,6 +118,15 @@ Enum Name(abi_base) Type(int) Base ABI types for LoongArch: +EnumValue +Enum(abi_base) String(ilp32d) Value(ABI_BASE_ILP32D) + +EnumValue +Enum(abi_base) String(ilp32f) Value(ABI_BASE_ILP32F) + +EnumValue +Enum(abi_base) String(ilp32s) Value(ABI_BASE_ILP32S) + EnumValue Enum(abi_base) String(lp64d) Value(ABI_BASE_LP64D) diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux index e40da179203..1718c3e11a2 100644 --- a/gcc/config/loongarch/t-linux +++ b/gcc/config/loongarch/t-linux @@ -17,8 +17,8 @@ # . # Multilib -MULTILIB_OPTIONS = mabi=lp64d/mabi=lp64f/mabi=lp64s -MULTILIB_DIRNAMES = base/lp64d base/lp64f base/lp64s +MULTILIB_OPTIONS = mabi=ilp32d/mabi=ilp32f/mabi=ilp32s/mabi=lp64d/mabi=lp64f/mabi=lp64s +MULTILIB_DIRNAMES = base/ilp32d base/ilp32f base/ilp32s base/lp64d base/lp64f base/lp64s # The GCC driver always gets all abi-related options on the command line. # (see loongarch-driver.c:driver_get_normalized_m_opts) @@ -38,6 +38,18 @@ endif # Don't define MULTILIB_OSDIRNAMES if multilib is disabled. ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),) + MULTILIB_OSDIRNAMES = \ + mabi.ilp32d=../lib32$\ + $(call if_multiarch,:loongarch32-linux-gnu) + + MULTILIB_OSDIRNAMES += \ + mabi.ilp32f=../lib32/f32$\ + $(call if_multiarch,:loongarch32-linux-gnuf32) + + MULTILIB_OSDIRNAMES += \ + mabi.ilp32s=../lib32/sf$\ + $(call if_multiarch,:loongarch32-linux-gnusf) + MULTILIB_OSDIRNAMES = \ mabi.lp64d=../lib64$\ $(call if_multiarch,:loongarch64-linux-gnu) From patchwork Wed Aug 9 11:46:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=idr8mD5+; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT486ccvz1yfB for ; Wed, 9 Aug 2023 21:54:16 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EA4753857737 for ; Wed, 9 Aug 2023 11:54:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EA4753857737 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582055; bh=GICcTj6nT+T9zVp+KmWtbQiPu0MhYNo0OepD5RnTgQE=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=idr8mD5++pxk+1UsljSm+kcu5/+5L/9+vIkpfc+h7+Chu68m5iyFt0bpHlbIzm3hq R3SuenfpQaPfGUbmZRx+opVcaK8WrKeGfHIo3yB+GGY7bYLmQ9U7tQPaYOn/xNX3P7 j52mQXxF7vouKhXYeawsBYQX0H39T0iBgJ5o5ayc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id E7AE4385828E for ; Wed, 9 Aug 2023 11:53:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E7AE4385828E Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id E460F44063; Wed, 9 Aug 2023 11:53:50 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 02/14] LoongArch: Fix default ISA setting Date: Wed, 9 Aug 2023 19:46:09 +0800 Message-ID: <20230809115325.3716347-3-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" When loongarch_arch_target is called, la_target has not been initialized, thus the macro LARCH_ACTUAL_ARCH always equals to zero. This commit fixes by expanding the macro and reading the latest value. It permits -march=loongarch64 when the default target is loongarch32 and vice versa. gcc/ChangeLog: * config/loongarch/loongarch-opts.cc (loongarch_config_target): Fix -march detection. gcc/testsuite/ChangeLog: * gcc.target/loongarch/arch-1.c: New test. * gcc.target/loongarch/arch-2.c: New test. --- gcc/config/loongarch/loongarch-opts.cc | 5 ++++- gcc/testsuite/gcc.target/loongarch/arch-1.c | 5 +++++ gcc/testsuite/gcc.target/loongarch/arch-2.c | 5 +++++ 3 files changed, 14 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/arch-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/arch-2.c diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 9fc0bbbcb6e..29c0c4468bb 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -246,7 +246,10 @@ loongarch_config_target (struct loongarch_target *target, config_target_isa: /* Get default ISA from "-march" or its default value. */ - t.isa = loongarch_cpu_default_isa[LARCH_ACTUAL_ARCH]; + if (t.cpu_arch == TARGET_ARCH_NATIVE) + t.isa = loongarch_cpu_default_isa[t.cpu_native]; + else + t.isa = loongarch_cpu_default_isa[t.cpu_arch]; /* Apply incremental changes. */ /* "-march=native" overrides the default FPU type. */ diff --git a/gcc/testsuite/gcc.target/loongarch/arch-1.c b/gcc/testsuite/gcc.target/loongarch/arch-1.c new file mode 100644 index 00000000000..379036ec76f --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/arch-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/loongarch/arch-2.c b/gcc/testsuite/gcc.target/loongarch/arch-2.c new file mode 100644 index 00000000000..55d646902a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/arch-2.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=loongarch32 -mabi=ilp32d" } */ +int foo() +{ +} From patchwork Wed Aug 9 11:46:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=vOESZGHK; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT6P1rdLz1yYC for ; Wed, 9 Aug 2023 21:56:13 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 340023851ABC for ; Wed, 9 Aug 2023 11:56:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 340023851ABC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582171; bh=hz9fQAMg3hlLjrkMm34K1SHrVQI5firXrWLUjigQLRs=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=vOESZGHK+OesM/4IEkXqMv5LThL6JLP3KnElJ6WbD2/B8wohhwKtkGE/DuyhtD5Op Sd/bp2rUyK3+0690cCArmC90l2RkA463vtOrDekLNJdTir4V4oBGjSggbUpNwOVl97 tp7ThhZzLy033CPWpAVKSgxxduQpIdJqdRptNpyg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id BAF153857B98 for ; Wed, 9 Aug 2023 11:53:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BAF153857B98 Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id B01EF4405F; Wed, 9 Aug 2023 11:53:52 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 03/14] LoongArch: Fix SI division for loongarch32 target Date: Wed, 9 Aug 2023 19:46:10 +0800 Message-ID: <20230809115325.3716347-4-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Add TARGET_64BIT check for loongarch64-only handling of SI division. It shall not promote SI to DI before division in loongarch32 target. gcc/ChangeLog: * config/loongarch/loongarch.md: Add TARGET_64BIT check for loongarch64-only handling of SI division. --- gcc/config/loongarch/loongarch.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index b37e070660f..95c5b25d22a 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -851,7 +851,7 @@ (match_operand:GPR 2 "register_operand")))] "" { - if (GET_MODE (operands[0]) == SImode) + if (GET_MODE (operands[0]) == SImode && TARGET_64BIT) { rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode); From patchwork Wed Aug 9 11:46:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819271 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=tVAq1giM; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT5F1kZmz1yYC for ; Wed, 9 Aug 2023 21:55:12 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6C9533852771 for ; Wed, 9 Aug 2023 11:55:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6C9533852771 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582110; bh=KwbhBmblqXqMpHQ1ZiGktdBC6W6WzjAglaoz95NlhdA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=tVAq1giMc+Web9IbgRUFeb800WpXOxzHCGxcDjDRhL+5LS8W8Wehj8fjAR/PkHuKJ oAHvbJ6+nhx+DiH+hfWB02EKMBb992AB8a0BUT1wiMJ5l/fQhzP0VZclbDQE2+0VJQ YOl37VaDAZaDxkK9bYqDGGPjIiXISj/bi4h6To+w= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 927B13857C41 for ; Wed, 9 Aug 2023 11:53:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 927B13857C41 Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 7E52D44026; Wed, 9 Aug 2023 11:53:54 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 04/14] LoongArch: Fix movgr2frh.w operand order Date: Wed, 9 Aug 2023 19:46:11 +0800 Message-ID: <20230809115325.3716347-5-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The operand order of movgr2frh.w was wrong. The correct order should be `movgr2frh.w fd, rj`. gcc/ChangeLog: * config/loongarch/loongarch.md (movgr2frh): Correct movgr2frh.w operand order. --- gcc/config/loongarch/loongarch.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 95c5b25d22a..93d8bf5bcca 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -2297,7 +2297,7 @@ (match_operand:SPLITF 2 "register_operand" "0")] UNSPEC_MOVGR2FRH))] "TARGET_DOUBLE_FLOAT" - "movgr2frh.w\t%z1,%0" + "movgr2frh.w\t%0,%z1" [(set_attr "move_type" "mgtf") (set_attr "mode" "")]) From patchwork Wed Aug 9 11:46:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=lakQGaIb; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT4T4f2Qz1yfB for ; Wed, 9 Aug 2023 21:54:32 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A7EDB3856964 for ; Wed, 9 Aug 2023 11:54:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A7EDB3856964 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582070; bh=tFO0fWd/9kr0f4oG8SGclzU3htv6Mlbv/ptQ3rQnUnE=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=lakQGaIb6XU4OXYc12h36MT+vvpqXv0d+amUeho/pewKDKcNFx/plLkb/pqvwhy2h nk0PaUG+0y2xBiX6I5JVUNKLIIknHA9rYIAZxZ0R5957d+ed+U+w6WdLRywenUhXZ/ yQntj5N+bhsp9aANtoi7d9hOpmQyp2x+ejtDjUXw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 760DE3858035 for ; Wed, 9 Aug 2023 11:53:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 760DE3858035 Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 589C843FAD; Wed, 9 Aug 2023 11:53:56 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 05/14] LoongArch: Fix 64-bit move for loongarch32 target Date: Wed, 9 Aug 2023 19:46:12 +0800 Message-ID: <20230809115325.3716347-6-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Bring back 64-bit move splitting for loongarch32. The code was removed in commit 16fc26d4e7a (`LoongArch: Support split symbol.`) for unknown reason. gcc/ChangeLog: * config/loongarch/loongarch.md: Handle move splitting for 64-bit operands. --- gcc/config/loongarch/loongarch.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 93d8bf5bcca..9eb6bb75c35 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1965,6 +1965,16 @@ [(set_attr "move_type" "move,load,store") (set_attr "mode" "DF")]) +(define_split + [(set (match_operand:MOVE64 0 "nonimmediate_operand") + (match_operand:MOVE64 1 "move_operand"))] + "reload_completed && loongarch_split_move_p (operands[0], operands[1])" + [(const_int 0)] +{ + loongarch_split_move (operands[0], operands[1], curr_insn); + DONE; +}) + ;; Emit a doubleword move in which exactly one of the operands is ;; a floating-point register. We can't just emit two normal moves ;; because of the constraints imposed by the FPU register model; From patchwork Wed Aug 9 11:46:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=vGeuIYgw; dkim-atps=neutral Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT6K40Xxz1yYC for ; Wed, 9 Aug 2023 21:56:09 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5DC4638560AA for ; Wed, 9 Aug 2023 11:56:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5DC4638560AA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582167; bh=qVQylrzwDUqA66goeLl/f6Z0Cn6pY0igX0Rfm6PDbxQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=vGeuIYgwQZHDzaPswRIZrJHUVVPb1KZKtDgRppEqyh/M2DhRSj4rbhDxz6LO95h6e A3y/j4vw5TTXRe+vJzUllM2+RkCIyOItGWL3o1hfGXMuNTQLCdXyMV2+ahnwIojoAU F1usbs3R0SJjA8gOx5x007cMKxmuuctDb4UXxz7k= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 6171D3857714 for ; Wed, 9 Aug 2023 11:54:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6171D3857714 Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 42CCE4402F; Wed, 9 Aug 2023 11:53:58 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 06/14] LoongArch: Fix 64-bit immediate move for loongarch32 target Date: Wed, 9 Aug 2023 19:46:13 +0800 Message-ID: <20230809115325.3716347-7-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" loongarch_move_integer does not support splitting 64-bit integer into two 32-bit ones. Thus, define_split is removed from movdi_32bit and TARGET_64BIT is added to the split condition of movdi_64bit to avoid using it for loongarch32. gcc/ChangeLog: * config/loongarch/loongarch.md (movdi_32bit): Remove not working split, use existing loongarch_split_move instead. (movdi_64bit): Add TARGET_64BIT to split condition. --- gcc/config/loongarch/loongarch.md | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 9eb6bb75c35..c611a8a822a 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1777,22 +1777,13 @@ DONE; }) -(define_insn_and_split "*movdi_32bit" +(define_insn "*movdi_32bit" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,w,*f,*f,*r,*m") (match_operand:DI 1 "move_operand" "r,i,w,r,*J*r,*m,*f,*f"))] "!TARGET_64BIT && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return loongarch_output_move (operands[0], operands[1]); } - "CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO - (operands[0]))" - [(const_int 0)] - " -{ - loongarch_move_integer (operands[0], operands[0], INTVAL (operands[1])); - DONE; -} - " [(set_attr "move_type" "move,const,load,store,mgtf,fpload,mftg,fpstore") (set_attr "mode" "DI")]) @@ -1804,7 +1795,7 @@ || reg_or_0_operand (operands[1], DImode))" { return loongarch_output_move (operands[0], operands[1]); } "CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO - (operands[0]))" + (operands[0])) && TARGET_64BIT" [(const_int 0)] " { From patchwork Wed Aug 9 11:46:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=SSsSYLQi; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT7R1txXz1yYC for ; Wed, 9 Aug 2023 21:57:07 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C9CA83831399 for ; Wed, 9 Aug 2023 11:57:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C9CA83831399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582224; bh=QQMHVki5kiJfU01pzQWZa1+SXZ5H01vdTAvCDlJiP0Y=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=SSsSYLQiPEIjmX/RajVUWeM5y1FxiFHQ6KmgoN1/QCUjl8kUC1qT/yNFE1VvzIxW6 C+ZJPzbyMHvssvTK4pDhysPyWd84hU/BZplmcSFRNRaZxRtVGhYIGlgtslX3Wjuvo6 dh+fAUyL/2W8Ycp+E3U/oCw6AQD7J/UVzZJNWhoI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 52F52385AC3A for ; Wed, 9 Aug 2023 11:54:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 52F52385AC3A Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 2C1F844026; Wed, 9 Aug 2023 11:53:59 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 07/14] LoongArch: Fix signed 32-bit overflow for loongarch32 target Date: Wed, 9 Aug 2023 19:46:14 +0800 Message-ID: <20230809115325.3716347-8-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" When rhs equals to 0x7fffffff, adding 1 to rhs overflows SI, generating invalid const_int. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_emit_int_compare): Call trunc_int_mode to ensure valid rhs. --- gcc/config/loongarch/loongarch.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index c980de98758..49df9509ba9 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -4284,6 +4284,7 @@ loongarch_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1) break; new_rhs = rhs + (increment ? 1 : -1); + new_rhs = trunc_int_for_mode (new_rhs, GET_MODE (*op0)); if (loongarch_integer_cost (new_rhs) < loongarch_integer_cost (rhs)) { From patchwork Wed Aug 9 11:46:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819278 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=ueclAPHH; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT7V12rkz1yYC for ; Wed, 9 Aug 2023 21:57:10 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2FCF53857B98 for ; Wed, 9 Aug 2023 11:57:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2FCF53857B98 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582228; bh=W+149kOXLVPnKYuIdTbqRu1++L9UxRWTIRLBI73cstg=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ueclAPHHKfG8sCDXwvYtjdYOYtnp0UGkCEjTG/7POpTXY2BmVkMuw+y3UpGN7qhiR DBYQmEBt20fdIIsqPXaRX3iszQ3xVy0L6b7ablYIECRYXvFxA0FDEDtlM58H8Q0qfq O5J+X1Gz/Q+E39LHmC8fthj0Py1SY7oLEOGHRUpk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 401CA385735E for ; Wed, 9 Aug 2023 11:54:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 401CA385735E Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 1EB9E43FAD; Wed, 9 Aug 2023 11:54:01 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 08/14] LoongArch: Disable SF/DF -> unsigned DI expand in loongarch32 Date: Wed, 9 Aug 2023 19:46:15 +0800 Message-ID: <20230809115325.3716347-9-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The current SF/DF -> unsigned DI expand rules require iordi3 insn which is not available in loongarch32. gcc/ChangeLog: * config/loongarch/loongarch.md (fixuns_truncdfdi2): Add TARGET_64BIT to condition. (fixuns_truncsfdi2): Add TARGET_64BIT to condition. --- gcc/config/loongarch/loongarch.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index c611a8a822a..31bdf3388f6 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1576,7 +1576,7 @@ (define_expand "fixuns_truncdfdi2" [(set (match_operand:DI 0 "register_operand") (unsigned_fix:DI (match_operand:DF 1 "register_operand")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" { rtx reg1 = gen_reg_rtx (DFmode); rtx reg2 = gen_reg_rtx (DFmode); @@ -1658,7 +1658,7 @@ (define_expand "fixuns_truncsfdi2" [(set (match_operand:DI 0 "register_operand") (unsigned_fix:DI (match_operand:SF 1 "register_operand")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" { rtx reg1 = gen_reg_rtx (SFmode); rtx reg2 = gen_reg_rtx (SFmode); From patchwork Wed Aug 9 11:46:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819279 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=djW/3bTN; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT8X0syXz1yYC for ; Wed, 9 Aug 2023 21:58:04 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 207123882ACC for ; Wed, 9 Aug 2023 11:58:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 207123882ACC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582282; bh=6tQG/BHS9X/W5qx7JTDfubpLV5dJ88FtQgYCSIDe/Ro=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=djW/3bTNfpnFMLokLnCuhFnGcWObcjGGV4qgXrOGk0IuOzxi6pN+rBt6w1xuGmzdd MbPmgNO3kP1CwDHxN5om2B84QhDPe3897zgcNdj7dm91qP3wMYj9NK3DSv13rXnaUU +2RI7Amb9YIuwqfD75DELTgVfSZ03FuSIKqlkKjM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 2A3A53857029 for ; Wed, 9 Aug 2023 11:54:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2A3A53857029 Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id EE61A4402F; Wed, 9 Aug 2023 11:54:03 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 09/14] LoongArch: Add -march=loongarch64 to tests with -mabi=lp64d Date: Wed, 9 Aug 2023 19:46:16 +0800 Message-ID: <20230809115325.3716347-10-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The compiler emits a warning if the current target (-march=loongarch32) mismatches with abi(-march=lp64d). Adding: Add -march=loongarch64 explicitly fixes the tests. gcc/testsuite/ChangeLog: * g++.target/loongarch/bytepick.C: Add -march=loongarch64 * g++.target/loongarch/pr106828.C: Add -march=loongarch64 * gcc.target/loongarch/add-const.c: Add -march=loongarch64 * gcc.target/loongarch/arch-1.c: Add -march=loongarch64 * gcc.target/loongarch/attr-model-1.c: Add -march=loongarch64 * gcc.target/loongarch/attr-model-2.c: Add -march=loongarch64 * gcc.target/loongarch/flt-abi-isa-1.c: Add -march=loongarch64 * gcc.target/loongarch/fscaleb.c: Add -march=loongarch64 * gcc.target/loongarch/ftint-no-inexact.c: Add -march=loongarch64 * gcc.target/loongarch/ftint.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-1.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-2.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-3.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-4.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-5.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-6.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-7.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-8.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-extreme-1.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-extreme-2.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-medium-1.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-medium-2.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-medium-3.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-medium-4.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-medium-5.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-medium-6.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-medium-7.c: Add -march=loongarch64 * gcc.target/loongarch/func-call-medium-8.c: Add -march=loongarch64 * gcc.target/loongarch/imm-load.c: Add -march=loongarch64 * gcc.target/loongarch/imm-load1.c: Add -march=loongarch64 * gcc.target/loongarch/mulw_d_w.c: Add -march=loongarch64 * gcc.target/loongarch/pr109465-1.c: Add -march=loongarch64 * gcc.target/loongarch/pr109465-2.c: Add -march=loongarch64 * gcc.target/loongarch/pr109465-3.c: Add -march=loongarch64 * gcc.target/loongarch/prolog-opt.c: Add -march=loongarch64 * gcc.target/loongarch/relocs-symbol-noaddend.c: Add -march=loongarch64 * gcc.target/loongarch/zero-size-field-pass.c: Add -march=loongarch64 * gcc.target/loongarch/zero-size-field-ret.c: Add -march=loongarch64 --- gcc/testsuite/g++.target/loongarch/bytepick.C | 2 +- gcc/testsuite/g++.target/loongarch/pr106828.C | 2 +- gcc/testsuite/gcc.target/loongarch/add-const.c | 2 +- gcc/testsuite/gcc.target/loongarch/attr-model-1.c | 2 +- gcc/testsuite/gcc.target/loongarch/attr-model-2.c | 2 +- gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c | 2 +- gcc/testsuite/gcc.target/loongarch/fscaleb.c | 2 +- gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c | 2 +- gcc/testsuite/gcc.target/loongarch/ftint.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-1.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-2.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-3.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-4.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-5.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-6.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-7.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-8.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c | 2 +- gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c | 2 +- gcc/testsuite/gcc.target/loongarch/imm-load.c | 2 +- gcc/testsuite/gcc.target/loongarch/imm-load1.c | 2 +- gcc/testsuite/gcc.target/loongarch/mulw_d_w.c | 2 +- gcc/testsuite/gcc.target/loongarch/pr109465-1.c | 2 +- gcc/testsuite/gcc.target/loongarch/pr109465-2.c | 2 +- gcc/testsuite/gcc.target/loongarch/pr109465-3.c | 2 +- gcc/testsuite/gcc.target/loongarch/prolog-opt.c | 2 +- gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c | 2 +- gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c | 2 +- gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c | 2 +- 37 files changed, 37 insertions(+), 37 deletions(-) diff --git a/gcc/testsuite/g++.target/loongarch/bytepick.C b/gcc/testsuite/g++.target/loongarch/bytepick.C index a39e2fa65b7..c2b0dd5e513 100644 --- a/gcc/testsuite/g++.target/loongarch/bytepick.C +++ b/gcc/testsuite/g++.target/loongarch/bytepick.C @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mabi=lp64d" } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */ /* { dg-final { scan-assembler-times "bytepick.w\t\\\$r4,\\\$r5,\\\$r4" 3 } } */ /* { dg-final { scan-assembler-times "bytepick.d\t\\\$r4,\\\$r5,\\\$r4" 7 } } */ /* { dg-final { scan-assembler-not "slli.w" } } */ diff --git a/gcc/testsuite/g++.target/loongarch/pr106828.C b/gcc/testsuite/g++.target/loongarch/pr106828.C index 190c1db715f..74590891a67 100644 --- a/gcc/testsuite/g++.target/loongarch/pr106828.C +++ b/gcc/testsuite/g++.target/loongarch/pr106828.C @@ -1,4 +1,4 @@ /* { dg-do-preprocess } */ -/* { dg-options "-mabi=lp64d -fsanitize=address" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -fsanitize=address" } */ /* Tests whether the compiler supports compile option '-fsanitize=address'. */ diff --git a/gcc/testsuite/gcc.target/loongarch/add-const.c b/gcc/testsuite/gcc.target/loongarch/add-const.c index 7b6a7cb92aa..04286afad49 100644 --- a/gcc/testsuite/gcc.target/loongarch/add-const.c +++ b/gcc/testsuite/gcc.target/loongarch/add-const.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O -mabi=lp64d" } */ +/* { dg-options "-O -march=loongarch64 -mabi=lp64d" } */ /* None of these functions should load the const operand into a temp register. */ diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-1.c b/gcc/testsuite/gcc.target/loongarch/attr-model-1.c index 916d715b98b..005c7cd727e 100644 --- a/gcc/testsuite/gcc.target/loongarch/attr-model-1.c +++ b/gcc/testsuite/gcc.target/loongarch/attr-model-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mexplicit-relocs -mcmodel=normal -O2" } */ +/* { dg-options "-mexplicit-relocs -mcmodel=normal -O2 -march=loongarch64" } */ /* { dg-final { scan-assembler-times "%pc64_hi12" 2 } } */ #define ATTR_MODEL_TEST diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-2.c b/gcc/testsuite/gcc.target/loongarch/attr-model-2.c index a74c795ac3e..242c40161e9 100644 --- a/gcc/testsuite/gcc.target/loongarch/attr-model-2.c +++ b/gcc/testsuite/gcc.target/loongarch/attr-model-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mexplicit-relocs -mcmodel=extreme -O2" } */ +/* { dg-options "-mexplicit-relocs -mcmodel=extreme -O2 -march=loongarch64" } */ /* { dg-final { scan-assembler-times "%pc64_hi12" 3 } } */ #define ATTR_MODEL_TEST diff --git a/gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c b/gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c index 1c9490f6a87..9cc2d439bf1 100644 --- a/gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c +++ b/gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -mfpu=64 -march=loongarch64 -O2" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -mfpu=64 -march=loongarch64 -O2" } */ /* { dg-final { scan-assembler "frecip\\.d" } } */ /* { dg-final { scan-assembler-not "movgr2fr\\.d" } } */ /* { dg-final { scan-assembler-not "movfr2gr\\.d" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/fscaleb.c b/gcc/testsuite/gcc.target/loongarch/fscaleb.c index f18470fbb8f..d39cdc63ae8 100644 --- a/gcc/testsuite/gcc.target/loongarch/fscaleb.c +++ b/gcc/testsuite/gcc.target/loongarch/fscaleb.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno" } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mdouble-float -fno-math-errno" } */ /* { dg-final { scan-assembler-times "fscaleb\\.s" 3 } } */ /* { dg-final { scan-assembler-times "fscaleb\\.d" 4 } } */ /* { dg-final { scan-assembler-times "slli\\.w" 1 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c b/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c index 88b83a9c056..e98d26070bc 100644 --- a/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c +++ b/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno -fno-fp-int-builtin-inexact" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -mdouble-float -fno-math-errno -fno-fp-int-builtin-inexact" } */ /* { dg-final { scan-assembler "ftint\\.l\\.s" } } */ /* { dg-final { scan-assembler "ftint\\.l\\.d" } } */ /* { dg-final { scan-assembler-not "ftintrm\\.l\\.s" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/ftint.c b/gcc/testsuite/gcc.target/loongarch/ftint.c index 7a326a454d8..1002293aee9 100644 --- a/gcc/testsuite/gcc.target/loongarch/ftint.c +++ b/gcc/testsuite/gcc.target/loongarch/ftint.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno -ffp-int-builtin-inexact" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -mdouble-float -fno-math-errno -ffp-int-builtin-inexact" } */ /* { dg-final { scan-assembler "ftint\\.l\\.s" } } */ /* { dg-final { scan-assembler "ftint\\.l\\.d" } } */ /* { dg-final { scan-assembler "ftintrm\\.l\\.s" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-1.c index 76bf11b0c03..d25a71e6a4c 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-1.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fplt -mno-explicit-relocs -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fplt -mno-explicit-relocs -mcmodel=normal" } */ /* { dg-final { scan-assembler "test:.*bl\t%plt\\(g\\)\n" } } */ /* { dg-final { scan-assembler "test1:.*bl\t%plt\\(f\\)\n" } } */ /* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-2.c index 4b468fef8b4..ac1d3b0cec2 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-2.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fplt -mno-explicit-relocs -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fplt -mno-explicit-relocs -mcmodel=normal" } */ /* { dg-final { scan-assembler "test:.*bl\t%plt\\(g\\)\n" } } */ /* { dg-final { scan-assembler "test1:.*bl\tf\n" } } */ /* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-3.c b/gcc/testsuite/gcc.target/loongarch/func-call-3.c index dd3a4882d60..e8156cb4eff 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-3.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mno-explicit-relocs -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mno-explicit-relocs -mcmodel=normal" } */ /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */ /* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-4.c b/gcc/testsuite/gcc.target/loongarch/func-call-4.c index f8158ec349f..684475bc3bb 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-4.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mno-explicit-relocs -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mno-explicit-relocs -mcmodel=normal" } */ /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*bl\tf\n" } } */ /* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-5.c b/gcc/testsuite/gcc.target/loongarch/func-call-5.c index 37994af430d..0411d8b6421 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-5.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fplt -mexplicit-relocs -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fplt -mexplicit-relocs -mcmodel=normal" } */ /* { dg-final { scan-assembler "test:.*bl\t%plt\\(g\\)\n" } } */ /* { dg-final { scan-assembler "test1:.*bl\t%plt\\(f\\)\n" } } */ /* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-6.c b/gcc/testsuite/gcc.target/loongarch/func-call-6.c index 8e366e376e7..beae892c8fd 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-6.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fplt -mexplicit-relocs -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fplt -mexplicit-relocs -mcmodel=normal" } */ /* { dg-final { scan-assembler "test:.*bl\t%plt\\(g\\)\n" } } */ /* { dg-final { scan-assembler "test1:.*bl\tf\n" } } */ /* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-7.c b/gcc/testsuite/gcc.target/loongarch/func-call-7.c index 4177c3d962e..6f6d0456836 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-7.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=normal" } */ /* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i\t.*%got_pc_hi20\\(f\\)\n\tld\.d\t.*%got_pc_lo12\\(f\\)\n\tjirl" } } */ /* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-8.c b/gcc/testsuite/gcc.target/loongarch/func-call-8.c index 4254eaa16d4..ebb68b368ed 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-8.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=normal" } */ /* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*bl\tf\n" } } */ /* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c index db1e0f85396..5e83d3107ed 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */ /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c index 21bf81ae837..e09defff24b 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */ /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c index 6339e832fe5..e43b4b0fe40 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fplt -mno-explicit-relocs -mcmodel=medium" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fplt -mno-explicit-relocs -mcmodel=medium" } */ /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */ /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c index a53e75e0bf9..17bfedd4d0d 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fplt -mno-explicit-relocs -mcmodel=medium" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fplt -mno-explicit-relocs -mcmodel=medium" } */ /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*la\.local\t.*f\n\tjirl" } } */ /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c index 0da7bf98e3c..00439c6ab9e 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mno-explicit-relocs -mcmodel=medium" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mno-explicit-relocs -mcmodel=medium" } */ /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */ /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c index 0219688ae80..ed23a4ebecc 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mno-explicit-relocs -mcmodel=medium" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mno-explicit-relocs -mcmodel=medium" } */ /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*la\.local\t.*f\n\tjirl" } } */ /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c index 8a47b5afcba..4693517843e 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fplt -mexplicit-relocs -mcmodel=medium" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fplt -mexplicit-relocs -mcmodel=medium" } */ /* { dg-final { scan-assembler "test:.*pcalau12i.*%pc_hi20\\(g\\)\n\tjirl.*pc_lo12\\(g\\)" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c index 1e75e60e01a..ef8228ec361 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fplt -mexplicit-relocs -mcmodel=medium" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fplt -mexplicit-relocs -mcmodel=medium" } */ /* { dg-final { scan-assembler "test:.*pcalau12i.*%pc_hi20\\(g\\)\n\tjirl.*pc_lo12\\(g\\)" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c index 9e89085ca19..12f2ef37b0e 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=medium" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=medium" } */ /* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i\t.*%got_pc_hi20\\(f\\)\n\tld\.d\t.*%got_pc_lo12\\(f\\)\n\tjirl" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i\t.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c index fde9c6e0ef4..251f207dfe0 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=medium" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=medium" } */ /* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i\t.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i\t.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/imm-load.c b/gcc/testsuite/gcc.target/loongarch/imm-load.c index c04ca33996f..18102efacde 100644 --- a/gcc/testsuite/gcc.target/loongarch/imm-load.c +++ b/gcc/testsuite/gcc.target/loongarch/imm-load.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O2 -fdump-rtl-split1" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -fdump-rtl-split1" } */ long int test (void) diff --git a/gcc/testsuite/gcc.target/loongarch/imm-load1.c b/gcc/testsuite/gcc.target/loongarch/imm-load1.c index 2ff02971239..4a0fe4fd30c 100644 --- a/gcc/testsuite/gcc.target/loongarch/imm-load1.c +++ b/gcc/testsuite/gcc.target/loongarch/imm-load1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O2" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O2" } */ /* { dg-final { scan-assembler "test:.*lu52i\.d.*\n\taddi\.w.*\n\.L2:" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c index 4ab7df8836b..0abe7b014b9 100644 --- a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c +++ b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mabi=lp64d" } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */ /* { dg-final { scan-assembler "mulw.d.w" } } */ /* This should be optimized to mulw.d.w for LA64. */ diff --git a/gcc/testsuite/gcc.target/loongarch/pr109465-1.c b/gcc/testsuite/gcc.target/loongarch/pr109465-1.c index 4cd35d13904..1f36f4e0ab6 100644 --- a/gcc/testsuite/gcc.target/loongarch/pr109465-1.c +++ b/gcc/testsuite/gcc.target/loongarch/pr109465-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mabi=lp64d -mno-strict-align" } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mno-strict-align" } */ /* { dg-final { scan-assembler-times "st\\.d|stptr\\.d" 1 } } */ /* { dg-final { scan-assembler-times "st\\.w|stptr\\.w" 1 } } */ /* { dg-final { scan-assembler-times "st\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/pr109465-2.c b/gcc/testsuite/gcc.target/loongarch/pr109465-2.c index 703eb951c6d..3e934567d0e 100644 --- a/gcc/testsuite/gcc.target/loongarch/pr109465-2.c +++ b/gcc/testsuite/gcc.target/loongarch/pr109465-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mabi=lp64d -mstrict-align" } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mstrict-align" } */ /* { dg-final { scan-assembler-times "st\\.d|stptr\\.d" 1 } } */ /* { dg-final { scan-assembler-times "st\\.w|stptr\\.w" 1 } } */ /* { dg-final { scan-assembler-times "st\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/pr109465-3.c b/gcc/testsuite/gcc.target/loongarch/pr109465-3.c index d6a80659b31..7c684b2a5bf 100644 --- a/gcc/testsuite/gcc.target/loongarch/pr109465-3.c +++ b/gcc/testsuite/gcc.target/loongarch/pr109465-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mabi=lp64d -mstrict-align" } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mstrict-align" } */ /* Three loop iterations each contains 4 st.b, and 3 st.b after the loop */ /* { dg-final { scan-assembler-times "st\\.b" 7 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/prolog-opt.c b/gcc/testsuite/gcc.target/loongarch/prolog-opt.c index e6a64263384..682d34ae750 100644 --- a/gcc/testsuite/gcc.target/loongarch/prolog-opt.c +++ b/gcc/testsuite/gcc.target/loongarch/prolog-opt.c @@ -1,7 +1,7 @@ /* Test that LoongArch backend stack drop operation optimized. */ /* { dg-do compile } */ -/* { dg-options "-O2 -mabi=lp64d -fno-stack-protector" } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -fno-stack-protector" } */ /* { dg-final { scan-assembler "addi.d\t\\\$r3,\\\$r3,-16" } } */ extern int printf (char *, ...); diff --git a/gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c b/gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c index 3ec8bd229fd..7d018ba0e4b 100644 --- a/gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c +++ b/gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -mexplicit-relocs -fno-pic -O2 -mcmodel=normal" } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -mexplicit-relocs -fno-pic -O2 -mcmodel=normal" } */ /* { dg-final { scan-assembler "pcalau12i.*%pc_hi20\\(\.LANCHOR0\\)\n" } } */ /* { dg-final { scan-assembler "addi\.d.*%pc_lo12\\(\.LANCHOR0\\)\n" } } */ /* { dg-final { scan-assembler "ldptr.d\t\\\$r4,.*,0\n" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c b/gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c index 999dc913a71..7931cc2623c 100644 --- a/gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c +++ b/gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c @@ -2,7 +2,7 @@ argument passing. */ /* { dg-do compile } */ -/* { dg-options "-O2 -mdouble-float -mabi=lp64d" } */ +/* { dg-options "-O2 -mdouble-float -march=loongarch64 -mabi=lp64d" } */ /* { dg-final { scan-assembler "\\\$f1" } } */ struct test diff --git a/gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c b/gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c index 40137d97555..ef1cb6b35c7 100644 --- a/gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c +++ b/gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c @@ -2,7 +2,7 @@ returning. */ /* { dg-do compile } */ -/* { dg-options "-O2 -mdouble-float -mabi=lp64d" } */ +/* { dg-options "-O2 -mdouble-float -march=loongarch64 -mabi=lp64d" } */ /* { dg-final { scan-assembler-not "\\\$r4" } } */ struct test From patchwork Wed Aug 9 11:46:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=yWk34XHM; dkim-atps=neutral Received: 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(unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id E9EE644026; Wed, 9 Aug 2023 11:54:05 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 10/14] LoongArch: Forbid ADDRESS_REG_REG in loongarch32 Date: Wed, 9 Aug 2023 19:46:17 +0800 Message-ID: <20230809115325.3716347-11-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" LoongArch32 does not include LDX/STD instructions, and cannot lower (plus (reg) (reg)) pattern. Forbid ADDRESS_REG_REG and do not emit ldx/stx. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_valid_index_p): Check ADDRESS_REG_REG pattern and fail in loongarch32. (loongarch_output_move_index): assertion failed if generating ldx/stx in loongarch32. gcc/testsuite/ChangeLog: * gcc.target/loongarch/array-ldx.c: Add regression test for ldx in loongarch32. --- gcc/config/loongarch/loongarch.cc | 4 +++- gcc/testsuite/gcc.target/loongarch/array-ldx.c | 6 ++++++ 2 files changed, 9 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/array-ldx.c diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 49df9509ba9..1fde680ccd4 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -2016,7 +2016,8 @@ loongarch_valid_index_p (struct loongarch_address_info *info, rtx x, && contains_reg_of_mode[GENERAL_REGS][GET_MODE (SUBREG_REG (index))]) index = SUBREG_REG (index); - if (loongarch_valid_base_register_p (index, mode, strict_p)) + /* LA32 does not provide LDX/STX. */ + if (loongarch_valid_base_register_p (index, mode, strict_p) && !TARGET_32BIT) { info->type = ADDRESS_REG_REG; info->offset = index; @@ -3853,6 +3854,7 @@ loongarch_output_move_index (rtx x, machine_mode mode, bool ldr) } }; + gcc_assert (!TARGET_32BIT); return insn[ldr][index]; } diff --git a/gcc/testsuite/gcc.target/loongarch/array-ldx.c b/gcc/testsuite/gcc.target/loongarch/array-ldx.c new file mode 100644 index 00000000000..0797af3bbfb --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/array-ldx.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=loongarch32 -mabi=ilp32d -O2" } */ +long long foo(long long *arr, long long index) +{ + return arr[index]; +} \ No newline at end of file From patchwork Wed Aug 9 11:46:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819283 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=O/gbvogH; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLTBh3nTKz1yYC for ; Wed, 9 Aug 2023 21:59:56 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7027B3856962 for ; Wed, 9 Aug 2023 11:59:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7027B3856962 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582394; bh=2zZ7uKhVzrWuWimYZUHi+qwQkYuVTA8lBCG9iqq/5Wc=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=O/gbvogHr82dMPkIWduBnX0YlAv915+GQE79/UIaiv+AQSNl6fVjMUNfSM9cJ8qzS WQ1Pt8HR2VQpsh3Jg4xFL45i/iYE6NrfhLTqHCjDNsUlb7h18cU18iwwgAzfXYeLJB MjWYVdDjYvYUgSLxg6GDeXg1kkCtfK2QI5LA923E= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 8C6B4385771C for ; Wed, 9 Aug 2023 11:54:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8C6B4385771C Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id CFFAD43FAD; Wed, 9 Aug 2023 11:54:07 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 11/14] LoongArch: Mark am* instructions as LA64-only Date: Wed, 9 Aug 2023 19:46:18 +0800 Message-ID: <20230809115325.3716347-12-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" LoongArch32 only provides basic ll/sc instructions for atomic operations. Mark am* atomic instructions as 64-bit only. gcc/ChangeLog: * config/loongarch.sync.md: Guard am* atomic insns by TARGET_64BIT. --- gcc/config/loongarch/sync.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index 9924d522bcd..151b553bcc6 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -77,7 +77,7 @@ [(match_operand:GPR 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] - "" + "TARGET_64BIT" "amswap%A2.\t$zero,%z1,%0" [(set (attr "length") (const_int 8))]) @@ -88,7 +88,7 @@ (match_operand:GPR 1 "reg_or_0_operand" "rJ")) (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "" + "TARGET_64BIT" "am%A2.\t$zero,%z1,%0" [(set (attr "length") (const_int 8))]) @@ -101,7 +101,7 @@ (match_operand:GPR 2 "reg_or_0_operand" "rJ")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "" + "TARGET_64BIT" "am%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 8))]) @@ -113,7 +113,7 @@ UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) (match_operand:GPR 2 "register_operand" "r"))] - "" + "TARGET_64BIT" "amswap%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 8))]) @@ -182,7 +182,7 @@ [(match_operand:QI 0 "register_operand" "") ;; bool output (match_operand:QI 1 "memory_operand" "+ZB") ;; memory (match_operand:SI 2 "const_int_operand" "")] ;; model - "" + "TARGET_64BIT" { /* We have no QImode atomics, so use the address LSBs to form a mask, then use an aligned SImode atomic. */ From patchwork Wed Aug 9 11:46:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=xSwTrIBQ; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT5j1Q92z1yYC for ; Wed, 9 Aug 2023 21:55:37 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 14D6138319DE for ; Wed, 9 Aug 2023 11:55:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 14D6138319DE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582135; bh=ffUlg7kBtdWhRVpAByeQ/m5U+EN0PQhpc+kDIHCgHnY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=xSwTrIBQAOyWVxpGq5r3z2AZl65+z2puCuqoyGUe/Dfk1kLLy1iFiQTZUf1UE0xzq zihYycWtVCUNCgkx4hCEXtloIgAEQxc7Uf2tbwlZF4tcLpH3J94ayfvPHGLYMRpv2p FoTamJNCF6D0lT9vM2M82ygfXZD13S+/Zqvmqrcs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id C88783858291 for ; Wed, 9 Aug 2023 11:54:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C88783858291 Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id B255444098; Wed, 9 Aug 2023 11:54:09 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 12/14] LoongArch: Set long double width to 128 in la32 Date: Wed, 9 Aug 2023 19:46:19 +0800 Message-ID: <20230809115325.3716347-13-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" According to latest loongarch procedure call standard, sizeof(long double) == 128 in ilp32 data model regardless of target bitness. gcc/ChangeLog: * config/loongarch/loongarch.h: Set LONG_DOUBLE_TYPE_SIZE to 128 regardless of target bitness. --- gcc/config/loongarch/loongarch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h index eca723293a1..ab0c80c69c1 100644 --- a/gcc/config/loongarch/loongarch.h +++ b/gcc/config/loongarch/loongarch.h @@ -205,7 +205,7 @@ along with GCC; see the file COPYING3. If not see #define FLOAT_TYPE_SIZE 32 #define DOUBLE_TYPE_SIZE 64 -#define LONG_DOUBLE_TYPE_SIZE (TARGET_64BIT ? 128 : 64) +#define LONG_DOUBLE_TYPE_SIZE 128 /* Define the sizes of fixed-point types. */ #define SHORT_FRACT_TYPE_SIZE 8 From patchwork Wed Aug 9 11:46:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819280 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=pY2a0Xbr; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT8g3DlWz1yYC for ; Wed, 9 Aug 2023 21:58:11 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B0D193830B6F for ; Wed, 9 Aug 2023 11:58:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B0D193830B6F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582288; bh=Zld2j/f8iNj5b31D1NvssSD5lvA5hDmbNsrUaY/Cr/A=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=pY2a0Xbr/ipeM3p6uoXj2+3wtEGgupmusYD8AMKNr29nbtdV74m38tAfm0oT4rrEj E8FSZO+31B4kTyJaTX8GgshWHYd/i7YGp5wUX4kMN2fNCFpkO5j4xt5BcttE+sXwGR izdpIubcsv1LPYUREBkZsGdinj8G4rh8r+NpKxhw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id B8CC43857706 for ; Wed, 9 Aug 2023 11:54:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B8CC43857706 Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 91AD944026; Wed, 9 Aug 2023 11:54:11 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 13/14] LoongArch: Fix ilp32 detection Date: Wed, 9 Aug 2023 19:46:20 +0800 Message-ID: <20230809115325.3716347-14-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The correct ilp32 macro name is __loongarch_ilp32. libitm/ChangeLog: * config/loongarch/asm.h: Fix ilp32 detection. --- libitm/config/loongarch/asm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libitm/config/loongarch/asm.h b/libitm/config/loongarch/asm.h index 39e02b45f17..11d6d3c079e 100644 --- a/libitm/config/loongarch/asm.h +++ b/libitm/config/loongarch/asm.h @@ -30,7 +30,7 @@ # define GPR_S st.d # define SZ_GPR 8 # define ADDSP(si) addi.d $sp, $sp, si -#elif defined(__loongarch64_ilp32) +#elif defined(__loongarch_ilp32) # define GPR_L ld.w # define GPR_S st.w # define SZ_GPR 4 From patchwork Wed Aug 9 11:46:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiajie Chen X-Patchwork-Id: 1819282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=RvuOLU2E; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLT9k3s74z1yYC for ; Wed, 9 Aug 2023 21:59:06 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8659B382E692 for ; Wed, 9 Aug 2023 11:59:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8659B382E692 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691582344; bh=NRcn0VPDnClzav3LJz/hObw0eMYOr/KppI6zA8b7aDs=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=RvuOLU2E2Vio7paEZsiwKbnJPFJYlR+l0oa8omDsg9/FPHKlOWAJWwaGaTKaCz6s0 mBEEYnQuEJQ2PwHutie/ZMkuNscciNN4ZPJqGbAQhRLtxj5AHuJsumtymIDXwxE9g5 r4n3Vee23cs0WCVHhAeT7x0EmMj9rs1KxyrD1hnY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from hognose1.porkbun.com (hognose1.porkbun.com [35.82.102.206]) by sourceware.org (Postfix) with ESMTPS id 9750B3856943 for ; Wed, 9 Aug 2023 11:54:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9750B3856943 Received: from cslab-raptor.. (unknown [166.111.226.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: c@jia.je) by hognose1.porkbun.com (Postfix) with ESMTPSA id 8314143FAD; Wed, 9 Aug 2023 11:54:13 +0000 (UTC) To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, xuchenghua@loongson.cn, Jiajie Chen Subject: [PATCH v2 14/14] LoongArch: Allow ftintrz for DF->DI in loongarch32 Date: Wed, 9 Aug 2023 19:46:21 +0800 Message-ID: <20230809115325.3716347-15-c@jia.je> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115325.3716347-1-c@jia.je> References: <20230809115325.3716347-1-c@jia.je> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiajie Chen via Gcc-patches From: Jiajie Chen Reply-To: Jiajie Chen Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" In LoongArch, signed DF->DI conversion can be done if -mfpu=64 and -march=loongarch32. gcc/ChangeLog: * config/loongarch/loongarch.md (fix_trunc*2): Use ANYFI instead of GPR because it depends on fpu width instead of target bits. --- gcc/config/loongarch/loongarch.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 31bdf3388f6..f6042af25b7 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1482,11 +1482,11 @@ ;; conversion of a floating-point value to a integer -(define_insn "fix_trunc2" - [(set (match_operand:GPR 0 "register_operand" "=f") - (fix:GPR (match_operand:ANYF 1 "register_operand" "f")))] +(define_insn "fix_trunc2" + [(set (match_operand:ANYFI 0 "register_operand" "=f") + (fix:ANYFI (match_operand:ANYF 1 "register_operand" "f")))] "" - "ftintrz.. %0,%1" + "ftintrz.. %0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "")])