| Message ID | 20230525231740.2405092-1-juzhe.zhong@rivai.ai |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Fix zero-scratch-regs-3.c fail | expand |
Lgtm with a minor comment <juzhe.zhong@rivai.ai> 於 2023年5月26日 週五 07:18 寫道： > From: Juzhe-Zhong <juzhe.zhong@rivai.ai> > > Fix ICE of zero-scratch-regs-3.c: > bug.c:7:1: internal compiler error: Segmentation fault > 7 | } > | ^ > 0x1647b23 crash_signal > ../../../riscv-gcc/gcc/toplev.cc:314 > 0x147053f maybe_legitimize_operand > ../../../riscv-gcc/gcc/optabs.cc:7947 > 0x1470dc2 maybe_legitimize_operands(insn_code, unsigned int, unsigned int, > expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8084 > 0x1470e66 maybe_gen_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8103 > 0x147146a maybe_expand_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8158 > 0x14714fe expand_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8189 > 0x1c20634 riscv_vector::insn_expander<11>::expand(insn_code, bool) > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:210 > 0x1c20075 riscv_vector::insn_expander<11>::emit_insn(insn_code, rtx_def**) > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:199 > 0x1c16bd1 riscv_vector::emit_vlmax_insn(unsigned int, int, rtx_def**, > rtx_def*) > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:362 > 0x1ad5bb9 vector_zero_call_used_regs > ../../../riscv-gcc/gcc/config/riscv/riscv.cc:7400 > 0x1ad5c25 riscv_zero_call_used_regs(HARD_REG_SET) > ../../../riscv-gcc/gcc/config/riscv/riscv.cc:7420 > 0x115c910 gen_call_used_regs_seq > ../../../riscv-gcc/gcc/function.cc:5924 > 0x115df81 execute > ../../../riscv-gcc/gcc/function.cc:6718 > > ICE happens since we didn't pass explicit VL operand when we can't use > gen_reg_rtx > to generate VL operand. This will make operands num mismatch. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (vector_zero_call_used_regs): Add explicit > VL operand. > > --- > gcc/config/riscv/riscv.cc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 09fc9e5d95e..9e41200371d 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -7398,7 +7398,7 @@ vector_zero_call_used_regs (HARD_REG_SET > need_zeroed_hardregs) > > rtx ops[] = {target, CONST0_RTX (mode), vl}; > Drop vl from here. riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), > - riscv_vector::RVV_UNOP, ops); > + riscv_vector::RVV_UNOP, ops, vl); > > SET_HARD_REG_BIT (zeroed_hardregs, regno); > } > -- > 2.36.3 > >
Committed the PATCH v2, thanks Kito. Pan -----Original Message----- From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Kito Cheng via Gcc-patches Sent: Friday, May 26, 2023 7:48 AM To: 钟居哲 <juzhe.zhong@rivai.ai> Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Jeff Law <jlaw@ventanamicro.com>; Jeff Law <jeffreyalaw@gmail.com>; Kito Cheng <kito.cheng@gmail.com>; Palmer Dabbelt <palmer@rivosinc.com> Subject: Re: [PATCH] RISC-V: Fix zero-scratch-regs-3.c fail Lgtm with a minor comment <juzhe.zhong@rivai.ai> 於 2023年5月26日 週五 07:18 寫道： > From: Juzhe-Zhong <juzhe.zhong@rivai.ai> > > Fix ICE of zero-scratch-regs-3.c: > bug.c:7:1: internal compiler error: Segmentation fault > 7 | } > | ^ > 0x1647b23 crash_signal > ../../../riscv-gcc/gcc/toplev.cc:314 > 0x147053f maybe_legitimize_operand > ../../../riscv-gcc/gcc/optabs.cc:7947 > 0x1470dc2 maybe_legitimize_operands(insn_code, unsigned int, unsigned > int, > expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8084 > 0x1470e66 maybe_gen_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8103 > 0x147146a maybe_expand_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8158 > 0x14714fe expand_insn(insn_code, unsigned int, expand_operand*) > ../../../riscv-gcc/gcc/optabs.cc:8189 > 0x1c20634 riscv_vector::insn_expander<11>::expand(insn_code, bool) > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:210 > 0x1c20075 riscv_vector::insn_expander<11>::emit_insn(insn_code, rtx_def**) > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:199 > 0x1c16bd1 riscv_vector::emit_vlmax_insn(unsigned int, int, rtx_def**, > rtx_def*) > ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:362 > 0x1ad5bb9 vector_zero_call_used_regs > ../../../riscv-gcc/gcc/config/riscv/riscv.cc:7400 > 0x1ad5c25 riscv_zero_call_used_regs(HARD_REG_SET) > ../../../riscv-gcc/gcc/config/riscv/riscv.cc:7420 > 0x115c910 gen_call_used_regs_seq > ../../../riscv-gcc/gcc/function.cc:5924 > 0x115df81 execute > ../../../riscv-gcc/gcc/function.cc:6718 > > ICE happens since we didn't pass explicit VL operand when we can't use > gen_reg_rtx to generate VL operand. This will make operands num > mismatch. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (vector_zero_call_used_regs): Add > explicit VL operand. > > --- > gcc/config/riscv/riscv.cc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 09fc9e5d95e..9e41200371d 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -7398,7 +7398,7 @@ vector_zero_call_used_regs (HARD_REG_SET > need_zeroed_hardregs) > > rtx ops[] = {target, CONST0_RTX (mode), vl}; > Drop vl from here. riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), > - riscv_vector::RVV_UNOP, ops); > + riscv_vector::RVV_UNOP, ops, > + vl); > > SET_HARD_REG_BIT (zeroed_hardregs, regno); > } > -- > 2.36.3 > >
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 09fc9e5d95e..9e41200371d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7398,7 +7398,7 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) rtx ops[] = {target, CONST0_RTX (mode), vl}; riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), - riscv_vector::RVV_UNOP, ops); + riscv_vector::RVV_UNOP, ops, vl); SET_HARD_REG_BIT (zeroed_hardregs, regno); }
From: Juzhe-Zhong <juzhe.zhong@rivai.ai> Fix ICE of zero-scratch-regs-3.c: bug.c:7:1: internal compiler error: Segmentation fault 7 | } | ^ 0x1647b23 crash_signal ../../../riscv-gcc/gcc/toplev.cc:314 0x147053f maybe_legitimize_operand ../../../riscv-gcc/gcc/optabs.cc:7947 0x1470dc2 maybe_legitimize_operands(insn_code, unsigned int, unsigned int, expand_operand*) ../../../riscv-gcc/gcc/optabs.cc:8084 0x1470e66 maybe_gen_insn(insn_code, unsigned int, expand_operand*) ../../../riscv-gcc/gcc/optabs.cc:8103 0x147146a maybe_expand_insn(insn_code, unsigned int, expand_operand*) ../../../riscv-gcc/gcc/optabs.cc:8158 0x14714fe expand_insn(insn_code, unsigned int, expand_operand*) ../../../riscv-gcc/gcc/optabs.cc:8189 0x1c20634 riscv_vector::insn_expander<11>::expand(insn_code, bool) ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:210 0x1c20075 riscv_vector::insn_expander<11>::emit_insn(insn_code, rtx_def**) ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:199 0x1c16bd1 riscv_vector::emit_vlmax_insn(unsigned int, int, rtx_def**, rtx_def*) ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:362 0x1ad5bb9 vector_zero_call_used_regs ../../../riscv-gcc/gcc/config/riscv/riscv.cc:7400 0x1ad5c25 riscv_zero_call_used_regs(HARD_REG_SET) ../../../riscv-gcc/gcc/config/riscv/riscv.cc:7420 0x115c910 gen_call_used_regs_seq ../../../riscv-gcc/gcc/function.cc:5924 0x115df81 execute ../../../riscv-gcc/gcc/function.cc:6718 ICE happens since we didn't pass explicit VL operand when we can't use gen_reg_rtx to generate VL operand. This will make operands num mismatch. gcc/ChangeLog: * config/riscv/riscv.cc (vector_zero_call_used_regs): Add explicit VL operand. --- gcc/config/riscv/riscv.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)