| Message ID | 20201112193114.7ED6633E80@hamza.pair.com |
|---|---|
| State | New |
| Headers | show |
| Series | [committed] wwwdocs: Editorial changes around x86-64 ISA extensions | expand |
On Fri, Nov 13, 2020 at 3:32 AM Gerald Pfeifer <gerald@pfeifer.com> wrote: > > Per our discussion on the list (plus a grammer improvement in a > section above). > > One question: why are the ISA extension lists not alphabetically > sorted? Wouldn't that be beneficial for users? Easier to find > something and also easier to compare? > Hmm, I just sorted them by the time they are enabled. When I changed the wwwdocs, I was referring to the previous gcc-8/changes.html, and didn't find that it was alphabetical. > Gerald > > --- > htdocs/gcc-11/changes.html | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html > index fc4c74f4..106db8e9 100644 > --- a/htdocs/gcc-11/changes.html > +++ b/htdocs/gcc-11/changes.html > @@ -265,7 +265,8 @@ a work-in-progress.</p> > </li> > <li>New ISA extension support for Intel AMX-TILE, AMX-INT8, AMX-BF16 was > added to GCC. AMX-TILE, AMX-INT8, AMX-BF16 intrinsics are available > - via the <code>-mamx-tile, -mamx-int8, -mamx-bf16</code> compiler switch. > + via the <code>-mamx-tile, -mamx-int8, -mamx-bf16</code> compiler > + switches. > </li> > <li>New ISA extension support for Intel AVX-VNNI was added to GCC. > AVX-VNNI intrinsics are available via the <code>-mavxvnni</code> > @@ -273,14 +274,14 @@ a work-in-progress.</p> > </li> > <li>GCC now supports the Intel CPU named Sapphire Rapids through > <code>-march=sapphirerapids</code>. > - The switch enables the MOVDIRI MOVDIR64B AVX512VP2INTERSECT ENQCMD CLDEMOTE > - SERIALIZE PTWRITE WAITPKG TSXLDTRK AMT-TILE AMX-INT8 AMX-BF16 AVX-VNNI > - ISA extensions. > + The switch enables the MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, > + CLDEMOTE, SERIALIZE, PTWRITE, WAITPKG, TSXLDTRK, AMT-TILE, AMX-INT8, > + AMX-BF16, and AVX-VNNI ISA extensions. > </li> > <li>GCC now supports the Intel CPU named Alderlake through > <code>-march=alderlake</code>. > - The switch enables the CLDEMOTE PTWRITE WAITPKG SERIALIZE KEYLOCKER AVX-VNNI > - HRESET ISA extensions. > + The switch enables the CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, > + AVX-VNNI, and HRESET ISA extensions. > </li> > </ul> > > -- > 2.29.2
diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html index fc4c74f4..106db8e9 100644 --- a/htdocs/gcc-11/changes.html +++ b/htdocs/gcc-11/changes.html @@ -265,7 +265,8 @@ a work-in-progress.</p> </li> <li>New ISA extension support for Intel AMX-TILE, AMX-INT8, AMX-BF16 was added to GCC. AMX-TILE, AMX-INT8, AMX-BF16 intrinsics are available - via the <code>-mamx-tile, -mamx-int8, -mamx-bf16</code> compiler switch. + via the <code>-mamx-tile, -mamx-int8, -mamx-bf16</code> compiler + switches. </li> <li>New ISA extension support for Intel AVX-VNNI was added to GCC. AVX-VNNI intrinsics are available via the <code>-mavxvnni</code> @@ -273,14 +274,14 @@ a work-in-progress.</p> </li> <li>GCC now supports the Intel CPU named Sapphire Rapids through <code>-march=sapphirerapids</code>. - The switch enables the MOVDIRI MOVDIR64B AVX512VP2INTERSECT ENQCMD CLDEMOTE - SERIALIZE PTWRITE WAITPKG TSXLDTRK AMT-TILE AMX-INT8 AMX-BF16 AVX-VNNI - ISA extensions. + The switch enables the MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, + CLDEMOTE, SERIALIZE, PTWRITE, WAITPKG, TSXLDTRK, AMT-TILE, AMX-INT8, + AMX-BF16, and AVX-VNNI ISA extensions. </li> <li>GCC now supports the Intel CPU named Alderlake through <code>-march=alderlake</code>. - The switch enables the CLDEMOTE PTWRITE WAITPKG SERIALIZE KEYLOCKER AVX-VNNI - HRESET ISA extensions. + The switch enables the CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, + AVX-VNNI, and HRESET ISA extensions. </li> </ul>