Some x86 AMD -march= docs fixes + formatting fixes (PR target/92962)

Hi!

The bug report complained just about missing RDPID and WBNOINVD in znver2
description and double comma before CLWB, but reading the docs I found
various other nits and when trying to compare it with what the compiler
actually does, I found ugly formatting there too.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

Note, it might be worth to introduce PTA_BTVER1 etc. in i386.h similarly
how it is done for Intel CPUs and set new CPU PTA_* masks incrementally from
that rather than then always including the whole set, could do that
incrementally if desired.

2019-12-17  Jakub Jelinek  <jakub@redhat.com>

	PR target/92962
	* common/config/i386/i386-common.c (processor_alias_table): Formatting
	fixes.
	* doc/invoke.texi (bdver3, bdver4, znver1): Add missing closing paren.
	(znver2): Likewise.  Add RDPID and WBNOINVD, remove spurious comma
	before CLWB.


	Jakub

On Tue, Dec 17, 2019 at 10:09 AM Jakub Jelinek <jakub@redhat.com> wrote:
>
> Hi!
>
> The bug report complained just about missing RDPID and WBNOINVD in znver2
> description and double comma before CLWB, but reading the docs I found
> various other nits and when trying to compare it with what the compiler
> actually does, I found ugly formatting there too.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> Note, it might be worth to introduce PTA_BTVER1 etc. in i386.h similarly
> how it is done for Intel CPUs and set new CPU PTA_* masks incrementally from
> that rather than then always including the whole set, could do that
> incrementally if desired.
>
> 2019-12-17  Jakub Jelinek  <jakub@redhat.com>
>
>         PR target/92962
>         * common/config/i386/i386-common.c (processor_alias_table): Formatting
>         fixes.
>         * doc/invoke.texi (bdver3, bdver4, znver1): Add missing closing paren.
>         (znver2): Likewise.  Add RDPID and WBNOINVD, remove spurious comma
>         before CLWB.

OK.

Thanks,
Uros.

> --- gcc/common/config/i386/i386-common.c.jj     2019-12-09 15:02:30.131287575 +0100
> +++ gcc/common/config/i386/i386-common.c        2019-12-16 22:26:44.477558339 +0100
> @@ -1617,7 +1617,7 @@ const pta processor_alias_table[] =
>    {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>      PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>    {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
> -    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>    {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>      PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>    {"prescott", PROCESSOR_NOCONA, CPU_NONE,
> @@ -1775,12 +1775,12 @@ const pta processor_alias_table[] =
>        | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
>        | PTA_WBNOINVD},
>    {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
> -    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
> -      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
>        | PTA_FXSR | PTA_XSAVE},
>    {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
> -    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
> -      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
>        | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>        | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>        | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
> --- gcc/doc/invoke.texi.jj      2019-12-13 11:36:01.140666243 +0100
> +++ gcc/doc/invoke.texi 2019-12-16 22:26:50.434467619 +0100
> @@ -27767,35 +27767,38 @@ instruction set extensions.)
>  CPUs based on AMD Family 15h cores with x86-64 instruction set support.  (This
>  supersets FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
>  SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
> +
>  @item bdver2
>  AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
>  supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX,
>  SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
>  extensions.)
> +
>  @item bdver3
>  AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
>  supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES,
>  PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and
> -64-bit instruction set extensions.
> +64-bit instruction set extensions.)
> +
>  @item bdver4
>  AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
>  supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP,
>  AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,
> -SSE4.2, ABM and 64-bit instruction set extensions.
> +SSE4.2, ABM and 64-bit instruction set extensions.)
>
>  @item znver1
>  AMD Family 17h core based CPUs with x86-64 instruction set support.  (This
>  supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX,
>  SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3,
>  SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
> -instruction set extensions.
> +instruction set extensions.)
> +
>  @item znver2
>  AMD Family 17h core based CPUs with x86-64 instruction set support. (This
> -supersets BMI, BMI2, ,CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,
> +supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,
>  MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
> -SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
> -instruction set extensions.)
> -
> +SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID,
> +WBNOINVD, and 64-bit instruction set extensions.)
>
>  @item btver1
>  CPUs based on AMD Family 14h cores with x86-64 instruction set support.  (This
>
>         Jakub
>