From patchwork Tue Dec 17 09:09:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 1211227 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-516088-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="HDgGEjH/"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="dTe5saxx"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47cXQP2cQgz9sRh for ; Tue, 17 Dec 2019 20:09:33 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type:content-transfer-encoding; q=dns; s=default; b=itr tdbZMrEFRU0WQFqzuXnfW6ZTG4Cdk4gEYQKXXoWX3lXRe1+G3WXVUCMQy+QP+djA tvoIGDWxfxVa6097Wn3XJ2p/ABCjB0y8I+5Q+OHln9AP0ZvaKQjy9QV4jr5h5V7P zQflJoLQMWTnza4Y6SaR87Q6iRoL40/ptrwY34Bg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type:content-transfer-encoding; s=default; bh=CsIbpzSJs 4LHAKAJHauIogjy2+I=; b=HDgGEjH/VmUuSmFRsPXKno4SLLtxOMQ+E7/mRKrtf 5xVWBTU1+s1dRJygE3f+5eZJ4c31pgfgBPIlEFFBIxzx5B3ILwn70cm66c51/Opc 7jonZ5vXR2a+rfBgD7OZqdEXKbh8ZOM7C70Vi4WaUzIvpeTl/IYvID74jNmNz0Mt yE= Received: (qmail 101460 invoked by alias); 17 Dec 2019 09:09:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 101443 invoked by uid 89); 17 Dec 2019 09:09:25 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=Family X-HELO: us-smtp-1.mimecast.com Received: from us-smtp-delivery-1.mimecast.com (HELO us-smtp-1.mimecast.com) (205.139.110.120) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 17 Dec 2019 09:09:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576573761; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=te4oZMQUfcToJMPSeMcsn6nMXuO3UPq8t/14Z98elyU=; b=dTe5saxx+9f5dkgav/nd3x9unoxmjIDo0FBMvPhnQeyeOCtMrECNOXz1iJPhN16ZUsaPX0 IQpkhklYlle2k0tNlEZIX7r00kdft8cm+S7OGqC12SC+IuO53xg7EBUQnDTtA7n8i6HnVh 9bsmqmrqWUeH+h1N9vUmN3wBy7Tph0I= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-288-gQ-zHAAtP6yVh1E8Kvjq0A-1; Tue, 17 Dec 2019 04:09:20 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4B703801E70; Tue, 17 Dec 2019 09:09:19 +0000 (UTC) Received: from tucnak.zalov.cz (ovpn-117-59.ams2.redhat.com [10.36.117.59]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D9A7B19427; Tue, 17 Dec 2019 09:09:18 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.15.2/8.15.2) with ESMTP id xBH99GAR008043; Tue, 17 Dec 2019 10:09:17 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.15.2/8.15.2/Submit) id xBH99Fpr008042; Tue, 17 Dec 2019 10:09:15 +0100 Date: Tue, 17 Dec 2019 10:09:15 +0100 From: Jakub Jelinek To: Uros Bizjak Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] Some x86 AMD -march= docs fixes + formatting fixes (PR target/92962) Message-ID: <20191217090915.GB10088@tucnak> Reply-To: Jakub Jelinek MIME-Version: 1.0 User-Agent: Mutt/1.11.3 (2019-02-01) X-Mimecast-Spam-Score: 0 Content-Disposition: inline X-IsSubscribed: yes Hi! The bug report complained just about missing RDPID and WBNOINVD in znver2 description and double comma before CLWB, but reading the docs I found various other nits and when trying to compare it with what the compiler actually does, I found ugly formatting there too. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? Note, it might be worth to introduce PTA_BTVER1 etc. in i386.h similarly how it is done for Intel CPUs and set new CPU PTA_* masks incrementally from that rather than then always including the whole set, could do that incrementally if desired. 2019-12-17 Jakub Jelinek PR target/92962 * common/config/i386/i386-common.c (processor_alias_table): Formatting fixes. * doc/invoke.texi (bdver3, bdver4, znver1): Add missing closing paren. (znver2): Likewise. Add RDPID and WBNOINVD, remove spurious comma before CLWB. Jakub --- gcc/common/config/i386/i386-common.c.jj 2019-12-09 15:02:30.131287575 +0100 +++ gcc/common/config/i386/i386-common.c 2019-12-16 22:26:44.477558339 +0100 @@ -1617,7 +1617,7 @@ const pta processor_alias_table[] = {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE, - PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR}, + PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR}, {"prescott", PROCESSOR_NOCONA, CPU_NONE, @@ -1775,12 +1775,12 @@ const pta processor_alias_table[] = | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID | PTA_WBNOINVD}, {"btver1", PROCESSOR_BTVER1, CPU_GENERIC, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE}, {"btver2", PROCESSOR_BTVER2, CPU_BTVER2, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1 + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT}, --- gcc/doc/invoke.texi.jj 2019-12-13 11:36:01.140666243 +0100 +++ gcc/doc/invoke.texi 2019-12-16 22:26:50.434467619 +0100 @@ -27767,35 +27767,38 @@ instruction set extensions.) CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This supersets FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) + @item bdver2 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) + @item bdver3 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and -64-bit instruction set extensions. +64-bit instruction set extensions.) + @item bdver4 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, -SSE4.2, ABM and 64-bit instruction set extensions. +SSE4.2, ABM and 64-bit instruction set extensions.) @item znver1 AMD Family 17h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit -instruction set extensions. +instruction set extensions.) + @item znver2 AMD Family 17h core based CPUs with x86-64 instruction set support. (This -supersets BMI, BMI2, ,CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, +supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, -SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit -instruction set extensions.) - +SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID, +WBNOINVD, and 64-bit instruction set extensions.) @item btver1 CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This