@@ -966,7 +966,6 @@ See RS/6000 and PowerPC Options.
@emph{RISC-V Options}
@gccoptlist{-mbranch-cost=@var{N-instruction} @gol
--mmemcpy -mno-memcpy @gol
-mplt -mno-plt @gol
-mabi=@var{ABI-string} @gol
-mfdiv -mno-fdiv @gol
@@ -976,7 +975,7 @@ See RS/6000 and PowerPC Options.
-msmall-data-limit=@var{N-bytes} @gol
-msave-restore -mno-save-restore @gol
-mstrict-align -mno-strict-align @gol
--mcmodel=@var{code-model} @gol
+-mcmodel=medlow -mcmodel=medany @gol
-mexplicit-relocs -mno-explicit-relocs @gol}
@emph{RL78 Options}
@@ -20885,32 +20884,46 @@ These command-line options are defined for RISC-V targets:
@opindex mbranch-cost
Set the cost of branches to roughly @var{n} instructions.
-@item -mmemcpy
-@itemx -mno-memcpy
-@opindex mmemcpy
-Don't optimize block moves.
-
@item -mplt
@itemx -mno-plt
@opindex plt
-When generating PIC code, allow the use of PLTs. Ignored for non-PIC.
+When generating PIC code, do or don't allow the use of PLTs. Ignored for
+non-PIC. The default is @option{-mplt}.
@item -mabi=@var{ABI-string}
@opindex mabi
-Specify integer and floating-point calling convention. This defaults to the
-natural calling convention: e.g.@ LP64 for RV64I, ILP32 for RV32I, LP64D for
-RV64G.
+Specify integer and floating-point calling convention. @var{ABI-string}
+contains two parts: the size of integer types and the registers used for
+floating-point types. For example @samp{-march=rv64ifd -mabi=lp64d} means that
+@samp{long} and pointers are 64-bit (implicitly defining @samp{int} to be
+32-bit), and that floating-point values up to 64 bits wide are passed in F
+registers. Contrast this with @samp{-march=rv64ifd -mabi=lp64f}, which still
+allows the compiler to generate code that uses the F and D extensions but only
+allows floating-point values up to 32 bits long to be passed in registers; or
+@samp{-march=rv64ifd -mabi=lp64}, in which no floating-point arguments will be
+passed in registers.
+
+The default for this argument is system dependent, users who want a specific
+calling convention should specify one explicitly. The valid calling
+conventions are: @samp{ilp32}, @samp{ilp32f}, @samp{ilp32d}, @samp{lp64},
+@samp{lp64f}, and @samp{lp64d}. Some calling conventions are impossible to
+implement on some ISAs: for example, @samp{-march=rv32if -mabi=ilp32d} is
+invalid because the ABI requires 64-bit values be passed in F registers, but F
+registers are only 32 bits wide.
@item -mfdiv
@itemx -mno-fdiv
@opindex mfdiv
-Use hardware floating-point divide and square root instructions. This requires
-the F or D extensions for floating-point registers.
+Do or don't use hardware floating-point divide and square root instructions.
+This requires the F or D extensions for floating-point registers. The default
+is to use them if the specified architecture has these instructions.
@item -mdiv
@itemx -mno-div
@opindex mdiv
-Use hardware instructions for integer division. This requires the M extension.
+Do or don't use hardware instructions for integer division. This requires the
+M extension. The default is to use them if the specified architecture has
+these instructions.
@item -march=@var{ISA-string}
@opindex march
@@ -20930,16 +20943,35 @@ Put global and static data smaller than @var{n} bytes into a special section
@item -msave-restore
@itemx -mno-save-restore
@opindex msave-restore
-Use smaller but slower prologue and epilogue code.
+Do or don't use smaller but slower prologue and epilogue code that uses
+library function calls. The default is to use fast inline prologues and
+epilogues.
@item -mstrict-align
@itemx -mno-strict-align
@opindex mstrict-align
-Do not generate unaligned memory accesses.
+Do not or do generate unaligned memory accesses. The default is set depending
+on whether the processor we are optimizing for supports fast unaligned access
+or not.
+
+@item -mcmodel=medlow
+@opindex mcmodel=medlow
+Generate code for the medium-low code model. The program and its statically
+defined symbols must lie within a single 2 GiB address range and must lie
+between absolute addresses @minus{}2 GiB and +2 GiB. Programs can be
+statically or dynamically linked. This is the default code model.
+
+@item -mcmodel=medany
+@opindex mcmodel=medany
+Generate code for the medium-any code model. The program and its statically
+defined symbols must be within any single 2 GiB address range. Programs can be
+statically or dynamically linked.
-@item -mcmodel=@var{code-model}
-@opindex mcmodel
-Specify the code model.
+@item -mexplicit-relocs
+@itemx -mno-exlicit-relocs
+Use or do not use assembler relocation operators when dealing with symbolic
+addresses. The alternative is to use assembler macros instead, which may
+limit optimization.
@end table
This backports 4 commits, so that the riscv user docs will be correct on the gcc-7 branch. Tested with gcc build, and looking at the gcc.info file to make sure it is correct. Committed. This is the last riscv patch I'm backporting to the gcc-7 branch, unless some new issue comes up. Jim gcc/ Backport from mainline 2017-11-30 Jim Wilson <jimw@sifive.com> * doc/invoke.texi (RISC-V Options): Delete nonexistent -mmemcpy and -mno-memcpy options. For -mplt, -mfdiv, -mdiv, -msave-restore, and -mstrict-align, add info on default value. Delete redundant lines for -mabi. Add missing -mexplicit-relocs docs. Backport from mainline 2017-11-01 Palmer Dabbelt <palmer@dabbelt.com> * doc/invoke.texi (RISC-V Options): Use "@minus{}2 GB", not "-2 GB". * doc/invoke.texi (RISC-V Options): Explicitly name the medlow and medany code models, and describe what they do. 2017-10-27 Palmer Dabbelt <palmer@dabbelt.com> PR target/82717 * doc/invoke.texi (RISC-V) <-mabi>: Correct and improve. --- gcc/doc/invoke.texi | 70 ++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 51 insertions(+), 19 deletions(-)