From patchwork Thu Nov 30 18:39:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 843146 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-468273-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="iZV2FQKV"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ynmQc2cMbz9sNw for ; Fri, 1 Dec 2017 05:39:20 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=yCVcpRbFQ4u3 fCyuo3rYqZZGeDrxruLl9fkR1t0TJv3wgy3lPYsEVEbyGFWy0HfqEPQKS/3T+u2m XCGU8K7ynasMGZkbqOLqUxdNkERSe/pRaYkqhn4WaCwOVPZFpppURuroEwIgZB0/ sjHGkJaZJHcRbqdLmb0u4RuANoKIdzM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=XmVw3pkBf2hdc7Nz4a mhozIMbs4=; b=iZV2FQKVo/M2Upva8DQUodGC2tLfVv2CsjeJ6W9TotRk1aeGT4 g1MEGRT1zjssai8QqglRIxl+0Nl15S8XMZsSDa7DH+9dx6Ql8iPw8ubSTX27zeSd tEXg+eSda0Neb3ZpZ8lOep4b7wFlNZVNZCvUS48N79gswruwAbQ65PVzA= Received: (qmail 29003 invoked by alias); 30 Nov 2017 18:39:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 28993 invoked by uid 89); 30 Nov 2017 18:39:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pl0-f52.google.com Received: from mail-pl0-f52.google.com (HELO mail-pl0-f52.google.com) (209.85.160.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 30 Nov 2017 18:39:09 +0000 Received: by mail-pl0-f52.google.com with SMTP id d21so4753477pll.1 for ; Thu, 30 Nov 2017 10:39:09 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=EtKnplNv10ybj4wHXbpIG4PO/166n/GTsL1jKtPOxS8=; b=DP320KDWQsSJD5WJU+RvLhjokCP+71cY64X78bJIhsxrWUflzsT7zhH3iiksKGg6NT B5sxBXlFkA6g1RY96dC+Awx+suApF2zstO5OW/7R6t6jEmQhOiqrvGud5wDV9jXYmMs8 Ms9YXzSQYNqaDZVJ/E/HppIzsB4KS5Gxq7uR2XMRiCCNir7pPZqYfvgoEeP2QS4kjQ31 W/4abZHbumROFsSqCvQdCJn+sxG9Op1a8ZO6tuoh60+njbyEQ6VvLYsi3F8BzJIwyb35 EOcQe4+Fmzw6LZGJR8SitmEqK4SxrFjiVy4AIjekvqlAU9gRTSw7hG/CId1nITKh4PNh V0bQ== X-Gm-Message-State: AJaThX6LahGOMEkdLhVTbKLQERHM1/MSPcEQa4LUDMiA+5kESueFY+6r FoAh0rqUxQoQ6/QYMa7g51O75TDPb2s= X-Google-Smtp-Source: AGs4zMbbHt1BKJAPOruifd86CYblRtHsXXH7jLhl6O+6OVk+7Ld04KZodgQCxo1lOjYDFVzeWNhbuw== X-Received: by 10.84.218.72 with SMTP id f8mr3639026plm.143.1512067147400; Thu, 30 Nov 2017 10:39:07 -0800 (PST) Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a13sm7620832pgd.5.2017.11.30.10.39.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Nov 2017 10:39:06 -0800 (PST) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH, gcc-7] Riscv doc fixes and improvements. Date: Thu, 30 Nov 2017 10:39:05 -0800 Message-Id: <20171130183905.7109-1-jimw@sifive.com> This backports 4 commits, so that the riscv user docs will be correct on the gcc-7 branch. Tested with gcc build, and looking at the gcc.info file to make sure it is correct. Committed. This is the last riscv patch I'm backporting to the gcc-7 branch, unless some new issue comes up. Jim gcc/ Backport from mainline 2017-11-30 Jim Wilson * doc/invoke.texi (RISC-V Options): Delete nonexistent -mmemcpy and -mno-memcpy options. For -mplt, -mfdiv, -mdiv, -msave-restore, and -mstrict-align, add info on default value. Delete redundant lines for -mabi. Add missing -mexplicit-relocs docs. Backport from mainline 2017-11-01 Palmer Dabbelt * doc/invoke.texi (RISC-V Options): Use "@minus{}2 GB", not "-2 GB". * doc/invoke.texi (RISC-V Options): Explicitly name the medlow and medany code models, and describe what they do. 2017-10-27 Palmer Dabbelt PR target/82717 * doc/invoke.texi (RISC-V) <-mabi>: Correct and improve. --- gcc/doc/invoke.texi | 70 ++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 51 insertions(+), 19 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9b1857c..7311c10 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -966,7 +966,6 @@ See RS/6000 and PowerPC Options. @emph{RISC-V Options} @gccoptlist{-mbranch-cost=@var{N-instruction} @gol --mmemcpy -mno-memcpy @gol -mplt -mno-plt @gol -mabi=@var{ABI-string} @gol -mfdiv -mno-fdiv @gol @@ -976,7 +975,7 @@ See RS/6000 and PowerPC Options. -msmall-data-limit=@var{N-bytes} @gol -msave-restore -mno-save-restore @gol -mstrict-align -mno-strict-align @gol --mcmodel=@var{code-model} @gol +-mcmodel=medlow -mcmodel=medany @gol -mexplicit-relocs -mno-explicit-relocs @gol} @emph{RL78 Options} @@ -20885,32 +20884,46 @@ These command-line options are defined for RISC-V targets: @opindex mbranch-cost Set the cost of branches to roughly @var{n} instructions. -@item -mmemcpy -@itemx -mno-memcpy -@opindex mmemcpy -Don't optimize block moves. - @item -mplt @itemx -mno-plt @opindex plt -When generating PIC code, allow the use of PLTs. Ignored for non-PIC. +When generating PIC code, do or don't allow the use of PLTs. Ignored for +non-PIC. The default is @option{-mplt}. @item -mabi=@var{ABI-string} @opindex mabi -Specify integer and floating-point calling convention. This defaults to the -natural calling convention: e.g.@ LP64 for RV64I, ILP32 for RV32I, LP64D for -RV64G. +Specify integer and floating-point calling convention. @var{ABI-string} +contains two parts: the size of integer types and the registers used for +floating-point types. For example @samp{-march=rv64ifd -mabi=lp64d} means that +@samp{long} and pointers are 64-bit (implicitly defining @samp{int} to be +32-bit), and that floating-point values up to 64 bits wide are passed in F +registers. Contrast this with @samp{-march=rv64ifd -mabi=lp64f}, which still +allows the compiler to generate code that uses the F and D extensions but only +allows floating-point values up to 32 bits long to be passed in registers; or +@samp{-march=rv64ifd -mabi=lp64}, in which no floating-point arguments will be +passed in registers. + +The default for this argument is system dependent, users who want a specific +calling convention should specify one explicitly. The valid calling +conventions are: @samp{ilp32}, @samp{ilp32f}, @samp{ilp32d}, @samp{lp64}, +@samp{lp64f}, and @samp{lp64d}. Some calling conventions are impossible to +implement on some ISAs: for example, @samp{-march=rv32if -mabi=ilp32d} is +invalid because the ABI requires 64-bit values be passed in F registers, but F +registers are only 32 bits wide. @item -mfdiv @itemx -mno-fdiv @opindex mfdiv -Use hardware floating-point divide and square root instructions. This requires -the F or D extensions for floating-point registers. +Do or don't use hardware floating-point divide and square root instructions. +This requires the F or D extensions for floating-point registers. The default +is to use them if the specified architecture has these instructions. @item -mdiv @itemx -mno-div @opindex mdiv -Use hardware instructions for integer division. This requires the M extension. +Do or don't use hardware instructions for integer division. This requires the +M extension. The default is to use them if the specified architecture has +these instructions. @item -march=@var{ISA-string} @opindex march @@ -20930,16 +20943,35 @@ Put global and static data smaller than @var{n} bytes into a special section @item -msave-restore @itemx -mno-save-restore @opindex msave-restore -Use smaller but slower prologue and epilogue code. +Do or don't use smaller but slower prologue and epilogue code that uses +library function calls. The default is to use fast inline prologues and +epilogues. @item -mstrict-align @itemx -mno-strict-align @opindex mstrict-align -Do not generate unaligned memory accesses. +Do not or do generate unaligned memory accesses. The default is set depending +on whether the processor we are optimizing for supports fast unaligned access +or not. + +@item -mcmodel=medlow +@opindex mcmodel=medlow +Generate code for the medium-low code model. The program and its statically +defined symbols must lie within a single 2 GiB address range and must lie +between absolute addresses @minus{}2 GiB and +2 GiB. Programs can be +statically or dynamically linked. This is the default code model. + +@item -mcmodel=medany +@opindex mcmodel=medany +Generate code for the medium-any code model. The program and its statically +defined symbols must be within any single 2 GiB address range. Programs can be +statically or dynamically linked. -@item -mcmodel=@var{code-model} -@opindex mcmodel -Specify the code model. +@item -mexplicit-relocs +@itemx -mno-exlicit-relocs +Use or do not use assembler relocation operators when dealing with symbolic +addresses. The alternative is to use assembler macros instead, which may +limit optimization. @end table