diff mbox

[i386] Introduce support for PKU instructions.

Message ID 20151222154258.GA36822@msticlxl57.ims.intel.com
State New
Headers show

Commit Message

Kirill Yukhin Dec. 22, 2015, 3:43 p.m. UTC 
Hello Uroš,
I (hopefully fixed all of inputs, thanks!

Updated patch for i386.md in the bottom,
rest patch is the same.

Bootstrap in progress. New tests pass.

Is it ok for trunk if bootstrap will pass?

On 20 Dec 11:56, Uros Bizjak wrote:
> > +(define_expand "rdpkru"
> > +  [(set (match_operand:SI 0 "register_operand")
> > +       (unspec:SI [(const_int 0)] UNSPEC_PKU))
> > +   (set (reg:SI CX_REG)
> > +       (const_int 0))
> > +   (clobber (reg:SI DX_REG))]
> > +  "TARGET_PKU"
> > +{
> > +  emit_move_insn (gen_rtx_REG (SImode, CX_REG), CONST0_RTX (SImode));
> > +  emit_insn (gen_rdpkru_2 (operands[0]));
> > +  DONE;
> > +})
> 
> You should use "parallel" to emit insn with several parallel
> expressions. So, in the preparation statements, you move const0 to a
> pseudo, so the RA will later use correct register. And please leave to
> the expander to emit the pattern.
> 
> > +(define_insn "rdpkru_2"
> > +  [(set (match_operand:SI 0 "register_operand" "=a")
> > +       (unspec:SI [(const_int 0)] UNSPEC_PKU))
> > +   (clobber (reg:SI DX_REG))
> > +   (use (reg:SI CX_REG))]
> > +  "TARGET_PKU"
> > +  "rdpkru"
> > +  [(set_attr "type" "other")])
> 
> Please do not use explicit hard registers. There are appropriate
> single-reg constraints available for use. Without seeing the
> documentation, I think the above should look like:
> 
> (define_insn "*rdpkru"
>   [(set (match_operand:SI 0 "register_operand" "=a")
>        (unspec:SI [(match_operand:SI 1 "register_operand" "c")] UNSPEC_PKU))
>    (clobber (rmatch_operand "register_operand "=d"))
>   "TARGET_PKU"
>   "rdpkru"
>   [(set_attr "type" "other")])
> 
> > +(define_expand "wrpkru"
> > +  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand")] UNSPECV_PKU)
> > +   (set (reg:SI CX_REG)
> > +       (const_int 0))
> > +   (set (reg:SI DX_REG)
> > +       (const_int 0))]
> > +  "TARGET_PKU"
> > +{
> > +  emit_move_insn (gen_rtx_REG (SImode, CX_REG), CONST0_RTX (SImode));
> > +  emit_move_insn (gen_rtx_REG (SImode, DX_REG), CONST0_RTX (SImode));
> > +  emit_insn (gen_wrpkru_2 (operands[0]));
> > +  DONE;
> > +})
> > +
> > +(define_insn "wrpkru_2"
> > +  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")] UNSPECV_PKU)
> > +   (use (reg:SI CX_REG))
> > +   (use (reg:SI DX_REG))]
> > +  "TARGET_PKU"
> > +  "wrpkru"
> > +  [(set_attr "type" "other")])
> >
> Please move all input operands to the insisde of the unspec, but it
> looks that this pattern is missing clobber, as in the above rdpkru
> pattern.
This isns does not clobber any register.

> 
> Uros.

--
Thanks, K
diff mbox

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 49b2216..f427ae3 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -193,6 +193,9 @@ 
   UNSPEC_BNDCU
   UNSPEC_BNDCN
   UNSPEC_MPX_FENCE
+
+  ;; For RDPKRU support
+  UNSPEC_PKU
 ])

 (define_c_enum "unspecv" [
@@ -268,6 +271,9 @@ 
   ;; For CLZERO support
   UNSPECV_CLZERO

+  ;; For WRPKRU support
+  UNSPECV_PKU
+
 ])

 ;; Constants to represent rounding modes in the ROUND instruction
@@ -19287,6 +19293,47 @@ 
   [(set_attr "type" "imov")
    (set_attr "mode" "<MODE>")])

+(define_expand "rdpkru"
+  [(set (match_operand:SI 2 "register_operand") (const_int 0))
+   (parallel [(set (match_operand:SI 0 "register_operand")
+                  (unspec:SI [(match_dup 2)] UNSPEC_PKU))
+             (clobber (match_operand:SI 1 "register_operand"))])]
+  "TARGET_PKU"
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = gen_reg_rtx (SImode);
+})
+
+(define_insn "*rdpkru_2"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+       (unspec:SI [(match_operand:SI 2 "register_operand" "c")] UNSPEC_PKU))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_PKU"
+  "rdpkru"
+  [(set_attr "type" "other")])
+
+(define_expand "wrpkru"
+  [(set (match_operand:SI 1 "register_operand")
+       (const_int 0))
+   (set (match_operand:SI 2 "register_operand")
+       (const_int 0))
+   (unspec_volatile:SI [(match_operand:SI 0 "register_operand")
+                       (match_dup 1)
+                       (match_dup 2)] UNSPECV_PKU)]
+  "TARGET_PKU"
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = gen_reg_rtx (SImode);
+})
+
+(define_insn "*wrpkru_2"
+  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")
+                       (match_operand:SI 1 "register_operand" "c")
+                       (match_operand:SI 2 "register_operand" "d")] UNSPECV_PKU)]
+  "TARGET_PKU"
+  "wrpkru"
+  [(set_attr "type" "other")])
+
 (include "mmx.md")
 (include "sse.md")
 (include "sync.md")