From patchwork Tue Dec 22 15:43:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 560131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6F898140BBF for ; Wed, 23 Dec 2015 02:43:46 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=bdb17egh; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:content-transfer-encoding:in-reply-to; q=dns; s= default; b=WCt85+Y2LIlnzwKih+XNpL4Y7GJ8hcuUo6yP91C3e9+a/IanZiW9i I81IP7PZouaMrxzAyygU3HOgb+p3mnXadAJNs3bHDyI+nAy9aa1gd+tIVYBb41D/ BWIZFzgghUtWu4Zk8i4ERDO2k5ViD7t6YEoOr9oNIWh2vGgvftldk8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:content-transfer-encoding:in-reply-to; s=default; bh=g7rF6/vDJu9XgEEUftdVjWN4UYo=; b=bdb17egh/qj9ezffNxnyzW8atxZZ L0h3XHreFvrCmrtJW8I/qjAoOD9O84Xox2Jmu9mCOOufPb7DIyt4Oh4L6ecCuEat a5Wgl0qXGvKv2qSA8sm6e1Us11bqK9eGoI+pgzGPJ/tKLLxX+vn1ccmR79Jv2qf5 0/hes4ptFjiJAHE= Received: (qmail 1982 invoked by alias); 22 Dec 2015 15:43:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 1967 invoked by uid 89); 22 Dec 2015 15:43:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=set_attr, define_insn, MODE, pku X-HELO: mail-ig0-f170.google.com Received: from mail-ig0-f170.google.com (HELO mail-ig0-f170.google.com) (209.85.213.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 22 Dec 2015 15:43:36 +0000 Received: by mail-ig0-f170.google.com with SMTP id ph11so62789202igc.1 for ; Tue, 22 Dec 2015 07:43:36 -0800 (PST) X-Received: by 10.50.73.67 with SMTP id j3mr26337746igv.9.1450799014466; Tue, 22 Dec 2015 07:43:34 -0800 (PST) Received: from msticlxl57.ims.intel.com (irdmzpr02-ext.ir.intel.com. [192.198.151.37]) by smtp.gmail.com with ESMTPSA id 84sm7506171ioh.3.2015.12.22.07.43.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Dec 2015 07:43:32 -0800 (PST) Date: Tue, 22 Dec 2015 18:43:01 +0300 From: Kirill Yukhin To: Uros Bizjak Cc: GCC Patches Subject: Re: [PATCH, i386] Introduce support for PKU instructions. Message-ID: <20151222154258.GA36822@msticlxl57.ims.intel.com> References: <20151218071537.GA43039@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes Hello Uroš, I (hopefully fixed all of inputs, thanks! Updated patch for i386.md in the bottom, rest patch is the same. Bootstrap in progress. New tests pass. Is it ok for trunk if bootstrap will pass? On 20 Dec 11:56, Uros Bizjak wrote: > > +(define_expand "rdpkru" > > + [(set (match_operand:SI 0 "register_operand") > > + (unspec:SI [(const_int 0)] UNSPEC_PKU)) > > + (set (reg:SI CX_REG) > > + (const_int 0)) > > + (clobber (reg:SI DX_REG))] > > + "TARGET_PKU" > > +{ > > + emit_move_insn (gen_rtx_REG (SImode, CX_REG), CONST0_RTX (SImode)); > > + emit_insn (gen_rdpkru_2 (operands[0])); > > + DONE; > > +}) > > You should use "parallel" to emit insn with several parallel > expressions. So, in the preparation statements, you move const0 to a > pseudo, so the RA will later use correct register. And please leave to > the expander to emit the pattern. > > > +(define_insn "rdpkru_2" > > + [(set (match_operand:SI 0 "register_operand" "=a") > > + (unspec:SI [(const_int 0)] UNSPEC_PKU)) > > + (clobber (reg:SI DX_REG)) > > + (use (reg:SI CX_REG))] > > + "TARGET_PKU" > > + "rdpkru" > > + [(set_attr "type" "other")]) > > Please do not use explicit hard registers. There are appropriate > single-reg constraints available for use. Without seeing the > documentation, I think the above should look like: > > (define_insn "*rdpkru" > [(set (match_operand:SI 0 "register_operand" "=a") > (unspec:SI [(match_operand:SI 1 "register_operand" "c")] UNSPEC_PKU)) > (clobber (rmatch_operand "register_operand "=d")) > "TARGET_PKU" > "rdpkru" > [(set_attr "type" "other")]) > > > +(define_expand "wrpkru" > > + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand")] UNSPECV_PKU) > > + (set (reg:SI CX_REG) > > + (const_int 0)) > > + (set (reg:SI DX_REG) > > + (const_int 0))] > > + "TARGET_PKU" > > +{ > > + emit_move_insn (gen_rtx_REG (SImode, CX_REG), CONST0_RTX (SImode)); > > + emit_move_insn (gen_rtx_REG (SImode, DX_REG), CONST0_RTX (SImode)); > > + emit_insn (gen_wrpkru_2 (operands[0])); > > + DONE; > > +}) > > + > > +(define_insn "wrpkru_2" > > + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")] UNSPECV_PKU) > > + (use (reg:SI CX_REG)) > > + (use (reg:SI DX_REG))] > > + "TARGET_PKU" > > + "wrpkru" > > + [(set_attr "type" "other")]) > > > Please move all input operands to the insisde of the unspec, but it > looks that this pattern is missing clobber, as in the above rdpkru > pattern. This isns does not clobber any register. > > Uros. --- Thanks, K diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 49b2216..f427ae3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -193,6 +193,9 @@ UNSPEC_BNDCU UNSPEC_BNDCN UNSPEC_MPX_FENCE + + ;; For RDPKRU support + UNSPEC_PKU ]) (define_c_enum "unspecv" [ @@ -268,6 +271,9 @@ ;; For CLZERO support UNSPECV_CLZERO + ;; For WRPKRU support + UNSPECV_PKU + ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -19287,6 +19293,47 @@ [(set_attr "type" "imov") (set_attr "mode" "")]) +(define_expand "rdpkru" + [(set (match_operand:SI 2 "register_operand") (const_int 0)) + (parallel [(set (match_operand:SI 0 "register_operand") + (unspec:SI [(match_dup 2)] UNSPEC_PKU)) + (clobber (match_operand:SI 1 "register_operand"))])] + "TARGET_PKU" +{ + operands[1] = gen_reg_rtx (SImode); + operands[2] = gen_reg_rtx (SImode); +}) + +(define_insn "*rdpkru_2" + [(set (match_operand:SI 0 "register_operand" "=a") + (unspec:SI [(match_operand:SI 2 "register_operand" "c")] UNSPEC_PKU)) + (clobber (match_operand:SI 1 "register_operand" "=d"))] + "TARGET_PKU" + "rdpkru" + [(set_attr "type" "other")]) + +(define_expand "wrpkru" + [(set (match_operand:SI 1 "register_operand") + (const_int 0)) + (set (match_operand:SI 2 "register_operand") + (const_int 0)) + (unspec_volatile:SI [(match_operand:SI 0 "register_operand") + (match_dup 1) + (match_dup 2)] UNSPECV_PKU)] + "TARGET_PKU" +{ + operands[1] = gen_reg_rtx (SImode); + operands[2] = gen_reg_rtx (SImode); +}) + +(define_insn "*wrpkru_2" + [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a") + (match_operand:SI 1 "register_operand" "c") + (match_operand:SI 2 "register_operand" "d")] UNSPECV_PKU)] + "TARGET_PKU" + "wrpkru" + [(set_attr "type" "other")]) + (include "mmx.md") (include "sse.md") (include "sync.md")