diff mbox

, PR 65569, Fix powerpc long double regression PF 65240 caused

Message ID 20150326000930.GA29138@ibm-tiger.the-meissners.org
State New
Headers show

Commit Message

Michael Meissner March 26, 2015, 12:09 a.m. UTC 
Pat Haugen runs a spec regression tester on various PowerPC boxes, and he
noticed that my fix for PR 65240 (the bug involving floating point constants
and -ffast-math under VSX) caused a regression in building the dealII benchmark
on power6x.  I looked into it, and discovered I had missed extenddftf2_fprs
relying on (const_double 0.0) being used in RTL code.  This works on VSX
systems, where you can use the XXLXOR instruction, but it does not work on
previous systems.

This patch fixes the problem.  I have bootstrapped and ran make check on a
power7 big endian system and a power8 little endian system.  On power7, the
following test had been failing, and is now fixed (it doesn't fail on power8):

	g++.dg/torture/pr58369.C

I have also built the power8-vsx, power7-vsx, power6x-altivec suite with no
failures.  I'm building power6x-scalar, and power5-scalar shortly.  Assuming
that the last two spec runs build without errors, can I apply the patch?

2015-03-25  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/65569
	* config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use
	XXLXOR to create 0.0.  On pre-VSX systems make sure the constant
	0.0 is correctly setup.
	(extenddftf2_internal): Likewise.

Comments

David Edelsohn March 26, 2015, 3:07 a.m. UTC | #1 
On Wed, Mar 25, 2015 at 8:09 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> Pat Haugen runs a spec regression tester on various PowerPC boxes, and he
> noticed that my fix for PR 65240 (the bug involving floating point constants
> and -ffast-math under VSX) caused a regression in building the dealII benchmark
> on power6x.  I looked into it, and discovered I had missed extenddftf2_fprs
> relying on (const_double 0.0) being used in RTL code.  This works on VSX
> systems, where you can use the XXLXOR instruction, but it does not work on
> previous systems.
>
> This patch fixes the problem.  I have bootstrapped and ran make check on a
> power7 big endian system and a power8 little endian system.  On power7, the
> following test had been failing, and is now fixed (it doesn't fail on power8):
>
>         g++.dg/torture/pr58369.C
>
> I have also built the power8-vsx, power7-vsx, power6x-altivec suite with no
> failures.  I'm building power6x-scalar, and power5-scalar shortly.  Assuming
> that the last two spec runs build without errors, can I apply the patch?
>
> 2015-03-25  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>         PR target/65569
>         * config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use
>         XXLXOR to create 0.0.  On pre-VSX systems make sure the constant
>         0.0 is correctly setup.
>         (extenddftf2_internal): Likewise.

Okay.

Thanks, David
diff mbox

Patch

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 221668)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -8357,16 +8357,21 @@  (define_expand "extenddftf2_fprs"
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 
    && TARGET_LONG_DOUBLE_128"
 {
-  operands[2] = CONST0_RTX (DFmode);
-  /* Generate GOT reference early for SVR4 PIC.  */
-  if (DEFAULT_ABI == ABI_V4 && flag_pic)
-    operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
+  /* VSX can create 0.0 directly, otherwise let rs6000_emit_move create
+     the proper constant.  */
+  if (TARGET_VSX)
+    operands[2] = CONST0_RTX (DFmode);
+  else
+    {
+      operands[2] = gen_reg_rtx (DFmode);
+      rs6000_emit_move (operands[2], CONST0_RTX (DFmode), DFmode);
+    }
 })
 
 (define_insn_and_split "*extenddftf2_internal"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
-       (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rm")))
-   (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,ws,d,&d,r")
+       (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,md,rm")))
+   (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,j,m,d,n"))]
   "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 
    && TARGET_LONG_DOUBLE_128"