From patchwork Thu Mar 26 00:09:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 454829 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5FE08140119 for ; Thu, 26 Mar 2015 11:09:44 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass reason="1024-bit key; unprotected key" header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=rU9e8nFi; dkim-adsp=none (unprotected policy); dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; q=dns; s= default; b=PRnYEYbKZW2DbhnYXbEjs1gA5Fb8KnUvik7biUb3wyelF6jmN9geU DCMb9vi5CE4Fb/FxBBKLlrEo20KrPTkBBo1QgYMGmfh3iCQYV0nM4fidhKT8YKWj SgR2PdajcUNbSJibJ6b6G7ZwDXVkHOtqTzwLDbBGhj86NCqa+wR6B8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; s= default; bh=nLvrR+2xUb1EnPs+RBYFUAb/Rro=; b=rU9e8nFi2awiFOBBc0Rz MDMStyiJ/4J3deSjE4ehGmQQODkNOwrS+4mGfOVBGnvw9cOcRnwKZduj6ZTrcfRj UsF6zAkdHxGC96fWDuv4VTPG3ELk4h6kTzelRliRDgxvQsyJCLAUdYnh82QBM5Pi 74j7RHns2mU5GzhJDc6t0ow= Received: (qmail 5233 invoked by alias); 26 Mar 2015 00:09:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5211 invoked by uid 89); 26 Mar 2015 00:09:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: e35.co.us.ibm.com Received: from e35.co.us.ibm.com (HELO e35.co.us.ibm.com) (32.97.110.153) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 26 Mar 2015 00:09:35 +0000 Received: from /spool/local by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 25 Mar 2015 18:09:32 -0600 Received: from b03cxnp07029.gho.boulder.ibm.com (b03cxnp07029.gho.boulder.ibm.com [9.17.130.16]) by d03dlp02.boulder.ibm.com (Postfix) with ESMTP id BE96E3E40047 for ; Wed, 25 Mar 2015 18:09:31 -0600 (MDT) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t2Q09VfH50462806 for ; Wed, 25 Mar 2015 17:09:31 -0700 Received: from d03av02.boulder.ibm.com (localhost [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t2Q09V7E021012 for ; Wed, 25 Mar 2015 18:09:31 -0600 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-111.usma.ibm.com [9.32.77.111]) by d03av02.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t2Q09U8l020981; Wed, 25 Mar 2015 18:09:31 -0600 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 82753429AF; Wed, 25 Mar 2015 20:09:30 -0400 (EDT) Date: Wed, 25 Mar 2015 20:09:30 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH], PR 65569, Fix powerpc long double regression PF 65240 caused Message-ID: <20150326000930.GA29138@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15032600-0013-0000-0000-000009A44D0F X-IsSubscribed: yes Pat Haugen runs a spec regression tester on various PowerPC boxes, and he noticed that my fix for PR 65240 (the bug involving floating point constants and -ffast-math under VSX) caused a regression in building the dealII benchmark on power6x. I looked into it, and discovered I had missed extenddftf2_fprs relying on (const_double 0.0) being used in RTL code. This works on VSX systems, where you can use the XXLXOR instruction, but it does not work on previous systems. This patch fixes the problem. I have bootstrapped and ran make check on a power7 big endian system and a power8 little endian system. On power7, the following test had been failing, and is now fixed (it doesn't fail on power8): g++.dg/torture/pr58369.C I have also built the power8-vsx, power7-vsx, power6x-altivec suite with no failures. I'm building power6x-scalar, and power5-scalar shortly. Assuming that the last two spec runs build without errors, can I apply the patch? 2015-03-25 Michael Meissner PR target/65569 * config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use XXLXOR to create 0.0. On pre-VSX systems make sure the constant 0.0 is correctly setup. (extenddftf2_internal): Likewise. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 221668) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -8357,16 +8357,21 @@ (define_expand "extenddftf2_fprs" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" { - operands[2] = CONST0_RTX (DFmode); - /* Generate GOT reference early for SVR4 PIC. */ - if (DEFAULT_ABI == ABI_V4 && flag_pic) - operands[2] = validize_mem (force_const_mem (DFmode, operands[2])); + /* VSX can create 0.0 directly, otherwise let rs6000_emit_move create + the proper constant. */ + if (TARGET_VSX) + operands[2] = CONST0_RTX (DFmode); + else + { + operands[2] = gen_reg_rtx (DFmode); + rs6000_emit_move (operands[2], CONST0_RTX (DFmode), DFmode); + } }) (define_insn_and_split "*extenddftf2_internal" - [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r") - (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rm"))) - (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,ws,d,&d,r") + (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,md,rm"))) + (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,j,m,d,n"))] "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"