| Message ID | 1452170857-23957-1-git-send-email-alan.lawrence@arm.com |
|---|---|
| State | New |
| Headers | show |
On 07/01/16 12:47, Alan Lawrence wrote: > Here's an updated version, also covering the min/max patterns I missed before. > I've now managed to do some testing with a stage 1 compiler, by compiling all > tests in gcc.dg/vect at -O2 -ftree-vectorize -mips3d -march=mips64r2 -mabi=n32 > $x -ffast-math -ffinite-math-only. > > There were no changes in which files compiled (871 did, some did not due to > libraries etc. missing in my stage 1 compiler), and no changes in any assembly > output. The patterns were triggered on: > > fast-math-vect-reduc-5.c, fast-math-vect-reduc-8.c, fast-math-vect-reduc-9.c, > no-fast-math-vect16.c, pr66142.c, vect-outer-fir-big-array.c, vect-outer-fir.c, > vect-outer-fir-lb-big-array.c, vect-outer-fir-lb.c, vect-reduc-10.c, > vect-reduc-6.c > > I realize this is not completely representative of a 'proper' test run, in > which different files are compiled with different options, but it provides > reasonable confidence that I'm not changing any code generation. > > OK for trunk? (stage 3?) Ping. > gcc/ChangeLog: > > * config/mips/mips-ps-3d.md (reduc_splus_v2sf): Remove. > (reduc_plus_scal_v2sf): New. > (reduc_smax_v2sf): Rename to... > (reduc_smax_scal_v2sf): ...here, make result SFmode, add vec_extract. > (reduc_smin_v2sf): Rename to... > (reduc_smin_scal_v2sf): ...here, make result SFmode, add vec_extract. > --- > gcc/config/mips/mips-ps-3d.md | 34 ++++++++++++++++++++++------------ > 1 file changed, 22 insertions(+), 12 deletions(-) > > diff --git a/gcc/config/mips/mips-ps-3d.md b/gcc/config/mips/mips-ps-3d.md > index 8bc7608..a93a2b9 100644 > --- a/gcc/config/mips/mips-ps-3d.md > +++ b/gcc/config/mips/mips-ps-3d.md > @@ -371,13 +371,17 @@ > [(set_attr "type" "fadd") > (set_attr "mode" "SF")]) > > -(define_insn "reduc_splus_v2sf" > - [(set (match_operand:V2SF 0 "register_operand" "=f") > - (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") > - (match_dup 1)] > - UNSPEC_ADDR_PS))] > +(define_expand "reduc_plus_scal_v2sf" > + [(match_operand:SF 0 "register_operand" "=f") > + (match_operand:V2SF 1 "register_operand" "f")] > "TARGET_HARD_FLOAT && TARGET_MIPS3D" > - "") > + { > + rtx temp = gen_reg_rtx (V2SFmode); > + emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1])); > + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; > + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); > + DONE; > + }) > > ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word > (define_insn "mips_cvt_pw_ps" > @@ -745,20 +749,26 @@ > DONE; > }) > > -(define_expand "reduc_smin_v2sf" > - [(match_operand:V2SF 0 "register_operand") > +(define_expand "reduc_smin_scal_v2sf" > + [(match_operand:SF 0 "register_operand") > (match_operand:V2SF 1 "register_operand")] > "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" > { > - mips_expand_vec_reduc (operands[0], operands[1], gen_sminv2sf3); > + rtx temp = gen_reg_rtx (V2SFmode); > + mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3); > + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; > + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); > DONE; > }) > > -(define_expand "reduc_smax_v2sf" > - [(match_operand:V2SF 0 "register_operand") > +(define_expand "reduc_smax_scal_v2sf" > + [(match_operand:SF 0 "register_operand") > (match_operand:V2SF 1 "register_operand")] > "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" > { > - mips_expand_vec_reduc (operands[0], operands[1], gen_smaxv2sf3); > + rtx temp = gen_reg_rtx (V2SFmode); > + mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3); > + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; > + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); > DONE; > }) >
Alan Lawrence <alan.lawrence@foss.arm.com> writes: > On 07/01/16 12:47, Alan Lawrence wrote: > > Here's an updated version, also covering the min/max patterns I missed > before. > > I've now managed to do some testing with a stage 1 compiler, by > > compiling all tests in gcc.dg/vect at -O2 -ftree-vectorize -mips3d > > -march=mips64r2 -mabi=n32 $x -ffast-math -ffinite-math-only. > > > > There were no changes in which files compiled (871 did, some did not > > due to libraries etc. missing in my stage 1 compiler), and no changes > > in any assembly output. The patterns were triggered on: > > > > fast-math-vect-reduc-5.c, fast-math-vect-reduc-8.c, > > fast-math-vect-reduc-9.c, no-fast-math-vect16.c, pr66142.c, > > vect-outer-fir-big-array.c, vect-outer-fir.c, > > vect-outer-fir-lb-big-array.c, vect-outer-fir-lb.c, vect-reduc-10.c, > > vect-reduc-6.c > > > > I realize this is not completely representative of a 'proper' test > > run, in which different files are compiled with different options, but > > it provides reasonable confidence that I'm not changing any code > generation. > > > > OK for trunk? (stage 3?) > > Ping. I don't have any particularly better way of testing this set up at the moment. The change looks OK to me. Catherine: Do you have anything you can test this on? If not then I think we just do the change on the basis of the testing Alan has done. Matthew > > > gcc/ChangeLog: > > > > * config/mips/mips-ps-3d.md (reduc_splus_v2sf): Remove. > > (reduc_plus_scal_v2sf): New. > > (reduc_smax_v2sf): Rename to... > > (reduc_smax_scal_v2sf): ...here, make result SFmode, add > vec_extract. > > (reduc_smin_v2sf): Rename to... > > (reduc_smin_scal_v2sf): ...here, make result SFmode, add > vec_extract. > > --- > > gcc/config/mips/mips-ps-3d.md | 34 ++++++++++++++++++++++----------- > - > > 1 file changed, 22 insertions(+), 12 deletions(-) > > > > diff --git a/gcc/config/mips/mips-ps-3d.md > > b/gcc/config/mips/mips-ps-3d.md index 8bc7608..a93a2b9 100644 > > --- a/gcc/config/mips/mips-ps-3d.md > > +++ b/gcc/config/mips/mips-ps-3d.md > > @@ -371,13 +371,17 @@ > > [(set_attr "type" "fadd") > > (set_attr "mode" "SF")]) > > > > -(define_insn "reduc_splus_v2sf" > > - [(set (match_operand:V2SF 0 "register_operand" "=f") > > - (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") > > - (match_dup 1)] > > - UNSPEC_ADDR_PS))] > > +(define_expand "reduc_plus_scal_v2sf" > > + [(match_operand:SF 0 "register_operand" "=f") > > + (match_operand:V2SF 1 "register_operand" "f")] > > "TARGET_HARD_FLOAT && TARGET_MIPS3D" > > - "") > > + { > > + rtx temp = gen_reg_rtx (V2SFmode); > > + emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1])); > > + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; > > + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); > > + DONE; > > + }) > > > > ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word > > (define_insn "mips_cvt_pw_ps" > > @@ -745,20 +749,26 @@ > > DONE; > > }) > > > > -(define_expand "reduc_smin_v2sf" > > - [(match_operand:V2SF 0 "register_operand") > > +(define_expand "reduc_smin_scal_v2sf" > > + [(match_operand:SF 0 "register_operand") > > (match_operand:V2SF 1 "register_operand")] > > "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" > > { > > - mips_expand_vec_reduc (operands[0], operands[1], gen_sminv2sf3); > > + rtx temp = gen_reg_rtx (V2SFmode); > > + mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3); rtx lane > > + = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; emit_insn > > + (gen_vec_extractv2sf (operands[0], temp, lane)); > > DONE; > > }) > > > > -(define_expand "reduc_smax_v2sf" > > - [(match_operand:V2SF 0 "register_operand") > > +(define_expand "reduc_smax_scal_v2sf" > > + [(match_operand:SF 0 "register_operand") > > (match_operand:V2SF 1 "register_operand")] > > "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" > > { > > - mips_expand_vec_reduc (operands[0], operands[1], gen_smaxv2sf3); > > + rtx temp = gen_reg_rtx (V2SFmode); > > + mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3); rtx lane > > + = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; emit_insn > > + (gen_vec_extractv2sf (operands[0], temp, lane)); > > DONE; > > }) > >
> -----Original Message----- > From: Matthew Fortune [mailto:Matthew.Fortune@imgtec.com] > Sent: Thursday, January 14, 2016 5:49 AM > To: Alan Lawrence; Moore, Catherine > Cc: gcc-patches@gcc.gnu.org > Subject: RE: [PATCH][MIPS] Migrate reduction optabs in mips-ps-3d.md > > Alan Lawrence <alan.lawrence@foss.arm.com> writes: > > On 07/01/16 12:47, Alan Lawrence wrote: > > > Here's an updated version, also covering the min/max patterns I > > > missed > > before. > > > I've now managed to do some testing with a stage 1 compiler, by > > > compiling all tests in gcc.dg/vect at -O2 -ftree-vectorize -mips3d > > > -march=mips64r2 -mabi=n32 $x -ffast-math -ffinite-math-only. > > > > > > There were no changes in which files compiled (871 did, some did not > > > due to libraries etc. missing in my stage 1 compiler), and no > > > changes in any assembly output. The patterns were triggered on: > > > > > > fast-math-vect-reduc-5.c, fast-math-vect-reduc-8.c, > > > fast-math-vect-reduc-9.c, no-fast-math-vect16.c, pr66142.c, > > > vect-outer-fir-big-array.c, vect-outer-fir.c, > > > vect-outer-fir-lb-big-array.c, vect-outer-fir-lb.c, vect-reduc-10.c, > > > vect-reduc-6.c > > > > > > I realize this is not completely representative of a 'proper' test > > > run, in which different files are compiled with different options, > > > but it provides reasonable confidence that I'm not changing any code > > generation. > > > > > > OK for trunk? (stage 3?) > > > > Ping. > > I don't have any particularly better way of testing this set up at the moment. > The change looks OK to me. > > Catherine: Do you have anything you can test this on? If not then I think we > just do the change on the basis of the testing Alan has done. > I don't have a suitable board. Alan, please go ahead and commit. Thanks, Catherine > > > > > > gcc/ChangeLog: > > > > > > * config/mips/mips-ps-3d.md (reduc_splus_v2sf): Remove. > > > (reduc_plus_scal_v2sf): New. > > > (reduc_smax_v2sf): Rename to... > > > (reduc_smax_scal_v2sf): ...here, make result SFmode, add > > vec_extract. > > > (reduc_smin_v2sf): Rename to... > > > (reduc_smin_scal_v2sf): ...here, make result SFmode, add > > vec_extract. > > > --- > > > gcc/config/mips/mips-ps-3d.md | 34 > > > ++++++++++++++++++++++----------- > > - > > > 1 file changed, 22 insertions(+), 12 deletions(-) > > > > > > diff --git a/gcc/config/mips/mips-ps-3d.md > > > b/gcc/config/mips/mips-ps-3d.md index 8bc7608..a93a2b9 100644 > > > --- a/gcc/config/mips/mips-ps-3d.md > > > +++ b/gcc/config/mips/mips-ps-3d.md > > > @@ -371,13 +371,17 @@ > > > [(set_attr "type" "fadd") > > > (set_attr "mode" "SF")]) > > > > > > -(define_insn "reduc_splus_v2sf" > > > - [(set (match_operand:V2SF 0 "register_operand" "=f") > > > - (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") > > > - (match_dup 1)] > > > - UNSPEC_ADDR_PS))] > > > +(define_expand "reduc_plus_scal_v2sf" > > > + [(match_operand:SF 0 "register_operand" "=f") > > > + (match_operand:V2SF 1 "register_operand" "f")] > > > "TARGET_HARD_FLOAT && TARGET_MIPS3D" > > > - "") > > > + { > > > + rtx temp = gen_reg_rtx (V2SFmode); > > > + emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1])); > > > + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; > > > + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); > > > + DONE; > > > + }) > > > > > > ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word > > > (define_insn "mips_cvt_pw_ps" > > > @@ -745,20 +749,26 @@ > > > DONE; > > > }) > > > > > > -(define_expand "reduc_smin_v2sf" > > > - [(match_operand:V2SF 0 "register_operand") > > > +(define_expand "reduc_smin_scal_v2sf" > > > + [(match_operand:SF 0 "register_operand") > > > (match_operand:V2SF 1 "register_operand")] > > > "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" > > > { > > > - mips_expand_vec_reduc (operands[0], operands[1], gen_sminv2sf3); > > > + rtx temp = gen_reg_rtx (V2SFmode); mips_expand_vec_reduc (temp, > > > + operands[1], gen_sminv2sf3); rtx lane = BYTES_BIG_ENDIAN ? > > > + const1_rtx : const0_rtx; emit_insn (gen_vec_extractv2sf > > > + (operands[0], temp, lane)); > > > DONE; > > > }) > > > > > > -(define_expand "reduc_smax_v2sf" > > > - [(match_operand:V2SF 0 "register_operand") > > > +(define_expand "reduc_smax_scal_v2sf" > > > + [(match_operand:SF 0 "register_operand") > > > (match_operand:V2SF 1 "register_operand")] > > > "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" > > > { > > > - mips_expand_vec_reduc (operands[0], operands[1], gen_smaxv2sf3); > > > + rtx temp = gen_reg_rtx (V2SFmode); mips_expand_vec_reduc (temp, > > > + operands[1], gen_smaxv2sf3); rtx lane = BYTES_BIG_ENDIAN ? > > > + const1_rtx : const0_rtx; emit_insn (gen_vec_extractv2sf > > > + (operands[0], temp, lane)); > > > DONE; > > > }) > > >
diff --git a/gcc/config/mips/mips-ps-3d.md b/gcc/config/mips/mips-ps-3d.md index 8bc7608..a93a2b9 100644 --- a/gcc/config/mips/mips-ps-3d.md +++ b/gcc/config/mips/mips-ps-3d.md @@ -371,13 +371,17 @@ [(set_attr "type" "fadd") (set_attr "mode" "SF")]) -(define_insn "reduc_splus_v2sf" - [(set (match_operand:V2SF 0 "register_operand" "=f") - (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") - (match_dup 1)] - UNSPEC_ADDR_PS))] +(define_expand "reduc_plus_scal_v2sf" + [(match_operand:SF 0 "register_operand" "=f") + (match_operand:V2SF 1 "register_operand" "f")] "TARGET_HARD_FLOAT && TARGET_MIPS3D" - "") + { + rtx temp = gen_reg_rtx (V2SFmode); + emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1])); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); + DONE; + }) ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word (define_insn "mips_cvt_pw_ps" @@ -745,20 +749,26 @@ DONE; }) -(define_expand "reduc_smin_v2sf" - [(match_operand:V2SF 0 "register_operand") +(define_expand "reduc_smin_scal_v2sf" + [(match_operand:SF 0 "register_operand") (match_operand:V2SF 1 "register_operand")] "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { - mips_expand_vec_reduc (operands[0], operands[1], gen_sminv2sf3); + rtx temp = gen_reg_rtx (V2SFmode); + mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); DONE; }) -(define_expand "reduc_smax_v2sf" - [(match_operand:V2SF 0 "register_operand") +(define_expand "reduc_smax_scal_v2sf" + [(match_operand:SF 0 "register_operand") (match_operand:V2SF 1 "register_operand")] "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { - mips_expand_vec_reduc (operands[0], operands[1], gen_smaxv2sf3); + rtx temp = gen_reg_rtx (V2SFmode); + mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); DONE; })