From patchwork Thu Jan 7 12:47:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 564273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C59C01402A8 for ; Thu, 7 Jan 2016 23:48:02 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Q431XZk7; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=wYlnUpkl/qidyv5HmTGnGN8FmLjrzaDkBguwug2frcvOpYJRN+afT xtYJOg7DVCZO1XXUyRjXRkrZn7Rh0mVOc/3X1QJonteKFWlIIAjgEjol5es3x+kG HlcTWyJrXpE+zTudku9QZNbkeriVHR9D4IA4Vlm6hIqE8m1o/HJd0o= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=gCtLU5hg2EuuFC8hUQEKBR2dc2s=; b=Q431XZk7xUB+NJHvQ0Ub jy34UDf/RTsrF/WX622QmeaRvW88/GPaaCT4u826dOAkVTh/UotEEEXZdw2rpf6d GAO9/Pw/65Y7fYjJVQtU997wvGINFctXQ7a6UYtpEPA4ofwiZs6HC5IStMT6O4sG +Q8Ta28ZRHE7Pfj9SKgTHr4= Received: (qmail 80273 invoked by alias); 7 Jan 2016 12:47:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 80259 invoked by uid 89); 7 Jan 2016 12:47:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.9 required=5.0 tests=AWL, BAYES_00, MEDICAL_SUBJECT, RP_MATCHES_RCVD, SPF_PASS autolearn=no version=3.3.2 spammy=37117, fadd, 1.9.1, Point X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 07 Jan 2016 12:47:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3945E49; Thu, 7 Jan 2016 04:47:19 -0800 (PST) Received: from arm.com (e105915-lin.emea.arm.com [10.2.206.30]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A49BE3F246; Thu, 7 Jan 2016 04:47:51 -0800 (PST) From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: matthew.fortune@imgtec.com, clm@codesourcery.com Subject: [PATCH][MIPS] Migrate reduction optabs in mips-ps-3d.md Date: Thu, 7 Jan 2016 12:47:37 +0000 Message-Id: <1452170857-23957-1-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1446561069-27527-1-git-send-email-alan.lawrence@arm.com> References: <1446561069-27527-1-git-send-email-alan.lawrence@arm.com> X-IsSubscribed: yes Here's an updated version, also covering the min/max patterns I missed before. I've now managed to do some testing with a stage 1 compiler, by compiling all tests in gcc.dg/vect at -O2 -ftree-vectorize -mips3d -march=mips64r2 -mabi=n32 $x -ffast-math -ffinite-math-only. There were no changes in which files compiled (871 did, some did not due to libraries etc. missing in my stage 1 compiler), and no changes in any assembly output. The patterns were triggered on: fast-math-vect-reduc-5.c, fast-math-vect-reduc-8.c, fast-math-vect-reduc-9.c, no-fast-math-vect16.c, pr66142.c, vect-outer-fir-big-array.c, vect-outer-fir.c, vect-outer-fir-lb-big-array.c, vect-outer-fir-lb.c, vect-reduc-10.c, vect-reduc-6.c I realize this is not completely representative of a 'proper' test run, in which different files are compiled with different options, but it provides reasonable confidence that I'm not changing any code generation. OK for trunk? (stage 3?) Cheers, Alan gcc/ChangeLog: * config/mips/mips-ps-3d.md (reduc_splus_v2sf): Remove. (reduc_plus_scal_v2sf): New. (reduc_smax_v2sf): Rename to... (reduc_smax_scal_v2sf): ...here, make result SFmode, add vec_extract. (reduc_smin_v2sf): Rename to... (reduc_smin_scal_v2sf): ...here, make result SFmode, add vec_extract. --- gcc/config/mips/mips-ps-3d.md | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/gcc/config/mips/mips-ps-3d.md b/gcc/config/mips/mips-ps-3d.md index 8bc7608..a93a2b9 100644 --- a/gcc/config/mips/mips-ps-3d.md +++ b/gcc/config/mips/mips-ps-3d.md @@ -371,13 +371,17 @@ [(set_attr "type" "fadd") (set_attr "mode" "SF")]) -(define_insn "reduc_splus_v2sf" - [(set (match_operand:V2SF 0 "register_operand" "=f") - (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") - (match_dup 1)] - UNSPEC_ADDR_PS))] +(define_expand "reduc_plus_scal_v2sf" + [(match_operand:SF 0 "register_operand" "=f") + (match_operand:V2SF 1 "register_operand" "f")] "TARGET_HARD_FLOAT && TARGET_MIPS3D" - "") + { + rtx temp = gen_reg_rtx (V2SFmode); + emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1])); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); + DONE; + }) ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word (define_insn "mips_cvt_pw_ps" @@ -745,20 +749,26 @@ DONE; }) -(define_expand "reduc_smin_v2sf" - [(match_operand:V2SF 0 "register_operand") +(define_expand "reduc_smin_scal_v2sf" + [(match_operand:SF 0 "register_operand") (match_operand:V2SF 1 "register_operand")] "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { - mips_expand_vec_reduc (operands[0], operands[1], gen_sminv2sf3); + rtx temp = gen_reg_rtx (V2SFmode); + mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); DONE; }) -(define_expand "reduc_smax_v2sf" - [(match_operand:V2SF 0 "register_operand") +(define_expand "reduc_smax_scal_v2sf" + [(match_operand:SF 0 "register_operand") (match_operand:V2SF 1 "register_operand")] "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { - mips_expand_vec_reduc (operands[0], operands[1], gen_smaxv2sf3); + rtx temp = gen_reg_rtx (V2SFmode); + mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); DONE; })