diff mbox

[AArch64,array_mode,6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size.

Message ID 1442308483-21714-7-git-send-email-alan.lawrence@arm.com
State New
Headers show

Commit Message

Alan Lawrence Sept. 15, 2015, 9:14 a.m. UTC 
Same logic as previous; this makes the 2-, 3-, and 4-lane expanders all follow the same pattern.

bootstrapped and check-gcc on aarch64-none-linux-gnu.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_simd_ld2r<mode>,
	aarch64_vec_load_lanesoi_lane<mode>,
	aarch64_vec_store_lanesoi_lane<mode): Change operand mode
	from <V_TWO_ELEM> to BLK.
	(aarch64_ld2r<mode>, aarch64_ld2_lane<mode>,
	aarch64_st2_lane<mode>): Generate MEM rtx with BLKmode, call
	set_mem_size.

	* config/aarch64/iterators.md (V_TWO_ELEM): Remove.
---
 gcc/config/aarch64/aarch64-simd.md | 20 ++++++++++----------
 gcc/config/aarch64/iterators.md    | 10 ----------
 2 files changed, 10 insertions(+), 20 deletions(-)

Comments

James Greenhalgh Sept. 15, 2015, 9:33 a.m. UTC | #1 
On Tue, Sep 15, 2015 at 10:14:41AM +0100, Alan Lawrence wrote:
> Same logic as previous; this makes the 2-, 3-, and 4-lane expanders all
> follow the same pattern.
> 
> bootstrapped and check-gcc on aarch64-none-linux-gnu.

OK.

Thanks,
James

> gcc/ChangeLog:
> 
> 	* config/aarch64/aarch64-simd.md (aarch64_simd_ld2r<mode>,
> 	aarch64_vec_load_lanesoi_lane<mode>,
> 	aarch64_vec_store_lanesoi_lane<mode): Change operand mode
> 	from <V_TWO_ELEM> to BLK.
> 	(aarch64_ld2r<mode>, aarch64_ld2_lane<mode>,
> 	aarch64_st2_lane<mode>): Generate MEM rtx with BLKmode, call
> 	set_mem_size.
> 
> 	* config/aarch64/iterators.md (V_TWO_ELEM): Remove.
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 11b5ded..f239ee7 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3928,7 +3928,7 @@ 
 
 (define_insn "aarch64_simd_ld2r<mode>"
   [(set (match_operand:OI 0 "register_operand" "=w")
-       (unspec:OI [(match_operand:<V_TWO_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
+       (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")
                    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
                   UNSPEC_LD2_DUP))]
   "TARGET_SIMD"
@@ -3938,7 +3938,7 @@ 
 
 (define_insn "aarch64_vec_load_lanesoi_lane<mode>"
   [(set (match_operand:OI 0 "register_operand" "=w")
-	(unspec:OI [(match_operand:<V_TWO_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
+	(unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")
 		    (match_operand:OI 2 "register_operand" "0")
 		    (match_operand:SI 3 "immediate_operand" "i")
 		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
@@ -3982,8 +3982,8 @@ 
 
 ;; RTL uses GCC vector extension indices, so flip only for assembly.
 (define_insn "aarch64_vec_store_lanesoi_lane<mode>"
-  [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
-	(unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w")
+  [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+	(unspec:BLK [(match_operand:OI 1 "register_operand" "w")
 		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
 		    (match_operand:SI 2 "immediate_operand" "i")]
 		   UNSPEC_ST2_LANE))]
@@ -4387,8 +4387,8 @@ 
    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
-  machine_mode mode = <V_TWO_ELEM>mode;
-  rtx mem = gen_rtx_MEM (mode, operands[1]);
+  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
 
   emit_insn (gen_aarch64_simd_ld2r<mode> (operands[0], mem));
   DONE;
@@ -4607,8 +4607,8 @@ 
 	(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
-  machine_mode mode = <V_TWO_ELEM>mode;
-  rtx mem = gen_rtx_MEM (mode, operands[1]);
+  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
 
   emit_insn (gen_aarch64_vec_load_lanesoi_lane<mode> (operands[0],
 						      mem,
@@ -4889,8 +4889,8 @@ 
   (match_operand:SI 2 "immediate_operand")]
   "TARGET_SIMD"
 {
-  machine_mode mode = <V_TWO_ELEM>mode;
-  rtx mem = gen_rtx_MEM (mode, operands[0]);
+  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2);
 
   emit_insn (gen_aarch64_vec_store_lanesoi_lane<mode> (mem,
 						       operands[1],
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 82cf295..12c626f 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -591,16 +591,6 @@ 
 			(V2SI "V16SI")  (V2SF "V16SF")
 			(DI   "V8DI")  (DF   "V8DF")])
 
-;; Mode of pair of elements for each vector mode, to define transfer
-;; size for structure lane/dup loads and stores.
-(define_mode_attr V_TWO_ELEM [(V8QI "HI")   (V16QI "HI")
-                              (V4HI "SI")   (V8HI "SI")
-                              (V2SI "V2SI") (V4SI "V2SI")
-                              (DI "V2DI")   (V2DI "V2DI")
-                              (V2SF "V2SF") (V4SF "V2SF")
-                              (V4HF "SF") (V8HF "SF")
-                              (DF "V2DI")   (V2DF "V2DI")])
-
 ;; Mode for atomic operation suffixes
 (define_mode_attr atomic_sfx
   [(QI "b") (HI "h") (SI "") (DI "")])