From patchwork Tue Sep 15 09:14:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 517751 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3C6E214017E for ; Tue, 15 Sep 2015 19:16:18 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=GScbA7Pa; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; q=dns; s=default; b=lDQ jZP4VJ/S8uoW6NMx9H72xmmrKpYjIHuvLa8H5q7UHhfXIiqoUaNTCp00Sa7bfMB5 m7kbVkRq2k5GSG91FZx7ORnCPtVlhulAqfeDCJJ6GilsyP0whwFPUAmSFKBm7oQE W7XE/K2F3LXZSvkMX/GhX977Cv/0NfoWEisx/Vdc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; s=default; bh=8Mk4U3SK/ H68oQ7g7qkexWHP/Ng=; b=GScbA7PaCFqaPcwhs0bfo/JHJwzRjtvARfNTTj3cK nQO5s8VV23Hk8B2MtQ67+fwwo7Ts/C/pvhLLQ5KdnVn8yz4YWGEMQGqohD7zsqKL pRdxr7reCTIfsGNE99iZVVlspfE3J3XAyG185s1WTeTK+inXlTO6njk6IrHHkyRF ZE= Received: (qmail 51456 invoked by alias); 15 Sep 2015 09:16:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 51441 invoked by uid 89); 15 Sep 2015 09:16:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 15 Sep 2015 09:16:09 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-24-2b5mwVb-R9W383xunOpkzQ-13; Tue, 15 Sep 2015 10:14:58 +0100 Received: from arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 15 Sep 2015 10:14:54 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com Subject: [PATCH][AArch64 array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size. Date: Tue, 15 Sep 2015 10:14:41 +0100 Message-Id: <1442308483-21714-7-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> References: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> X-MC-Unique: 2b5mwVb-R9W383xunOpkzQ-13 X-IsSubscribed: yes Same logic as previous; this makes the 2-, 3-, and 4-lane expanders all follow the same pattern. bootstrapped and check-gcc on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_simd_ld2r, aarch64_vec_load_lanesoi_lane, aarch64_vec_store_lanesoi_lane to BLK. (aarch64_ld2r, aarch64_ld2_lane, aarch64_st2_lane): Generate MEM rtx with BLKmode, call set_mem_size. * config/aarch64/iterators.md (V_TWO_ELEM): Remove. --- gcc/config/aarch64/aarch64-simd.md | 20 ++++++++++---------- gcc/config/aarch64/iterators.md | 10 ---------- 2 files changed, 10 insertions(+), 20 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 11b5ded..f239ee7 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3928,7 +3928,7 @@ (define_insn "aarch64_simd_ld2r" [(set (match_operand:OI 0 "register_operand" "=w") - (unspec:OI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD2_DUP))] "TARGET_SIMD" @@ -3938,7 +3938,7 @@ (define_insn "aarch64_vec_load_lanesoi_lane" [(set (match_operand:OI 0 "register_operand" "=w") - (unspec:OI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (match_operand:OI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] @@ -3982,8 +3982,8 @@ ;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "aarch64_vec_store_lanesoi_lane" - [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") - (unspec: [(match_operand:OI 1 "register_operand" "w") + [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:BLK [(match_operand:OI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST2_LANE))] @@ -4387,8 +4387,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); emit_insn (gen_aarch64_simd_ld2r (operands[0], mem)); DONE; @@ -4607,8 +4607,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); emit_insn (gen_aarch64_vec_load_lanesoi_lane (operands[0], mem, @@ -4889,8 +4889,8 @@ (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[0]); + rtx mem = gen_rtx_MEM (BLKmode, operands[0]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); emit_insn (gen_aarch64_vec_store_lanesoi_lane (mem, operands[1], diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 82cf295..12c626f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -591,16 +591,6 @@ (V2SI "V16SI") (V2SF "V16SF") (DI "V8DI") (DF "V8DF")]) -;; Mode of pair of elements for each vector mode, to define transfer -;; size for structure lane/dup loads and stores. -(define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI") - (V4HI "SI") (V8HI "SI") - (V2SI "V2SI") (V4SI "V2SI") - (DI "V2DI") (V2DI "V2DI") - (V2SF "V2SF") (V4SF "V2SF") - (V4HF "SF") (V8HF "SF") - (DF "V2DI") (V2DF "V2DI")]) - ;; Mode for atomic operation suffixes (define_mode_attr atomic_sfx [(QI "b") (HI "h") (SI "") (DI "")])