mbox series

[v2,0/4] RISC-V target attribute

Message ID 20231010041305.9111-1-kito.cheng@sifive.com
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Series RISC-V target attribute | expand

Message

Kito Cheng Oct. 10, 2023, 4:13 a.m. UTC 
This patch set implement target attribute for RISC-V target, which is similar to other target like x86 or ARM, let user able to set some local setting per function without changing global settings.

We support arch, tune and cpu first, and we will support other target attribute later, this version DOES NOT include multi-version function support yet, that is future work, probably work for GCC 15.

The full proposal is put in RISC-V C-API document[1], which has discussed with RISC-V LLVM community, so we have consistent syntax and semantics. 

[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35

v2 changelog:
- Resolve awk multi-dimensional issue.
- Tweak code format
- Tweak testcases

Comments

juzhe.zhong@rivai.ai Oct. 10, 2023, 9:56 a.m. UTC | #1 
LGTM on my side.
IMHO, we need to support attribute (rvv_vector_bits) which depend on this patch, am I right?

If yes, will you support this feature in GCC-14 release?



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-10-10 12:13
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong
Subject: [PATCH v2 0/4] RISC-V target attribute
This patch set implement target attribute for RISC-V target, which is similar to other target like x86 or ARM, let user able to set some local setting per function without changing global settings.
 
We support arch, tune and cpu first, and we will support other target attribute later, this version DOES NOT include multi-version function support yet, that is future work, probably work for GCC 15.
 
The full proposal is put in RISC-V C-API document[1], which has discussed with RISC-V LLVM community, so we have consistent syntax and semantics. 
 
[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35
 
v2 changelog:
- Resolve awk multi-dimensional issue.
- Tweak code format
- Tweak testcases