| Message ID | 320899457d15b85eb0b71edd566cae035d7e1f55.1459251929.git.cyrille.pitchen@atmel.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Tue, Mar 29, 2016 at 02:24:13PM +0200, Cyrille Pitchen wrote: > This patch adds a new optional DT property which enables an alternative > way of supporting memory size above 16MiB (128Mib). This new mechanism > translates the regular 3byte-address op codes into their 4byte-address > version whereas the old/default mecanism makes the SPI memory enter its > 4byte-address mode, which has annoying side effects for early bootloaders. > > We cannot discover at run time whether the SPI NOR memory supports the > 4byte-address op codes. For instance both Macronix MX25L25635E and > MX25L25673G share the same JEDEC ID (C22019 without any extension byte). > However the first one doesn't support 4byte-address op codes whereas the > second one does. > > Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> > --- > Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 11 +++++++++++ > 1 file changed, 11 insertions(+) Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 2c91c03e7eb0..3cf1b3cdafe8 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -66,6 +66,17 @@ Optional properties: Refer to your chips' datasheet to check if this is supported by your chip. +- spi-nor-4byte-opcodes: For memory size above 16MiB (128Mib), use the dedicated + 4byte-address opcodes instead of entering the 4byte + address mode. This mode changes the internal state of + the chip so may conflict with some early boot loaders, + which expect to use the regular (Fast) Read opcodes + with 3byte address. + However 4byte-address opcodes are not supported by all + chips and support for them cannot be detected at + runtime. Refer to you chip's datasheet to check if this + is supported by your chip. + Example: flash: m25p80@0 {
This patch adds a new optional DT property which enables an alternative way of supporting memory size above 16MiB (128Mib). This new mechanism translates the regular 3byte-address op codes into their 4byte-address version whereas the old/default mecanism makes the SPI memory enter its 4byte-address mode, which has annoying side effects for early bootloaders. We cannot discover at run time whether the SPI NOR memory supports the 4byte-address op codes. For instance both Macronix MX25L25635E and MX25L25673G share the same JEDEC ID (C22019 without any extension byte). However the first one doesn't support 4byte-address op codes whereas the second one does. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 11 +++++++++++ 1 file changed, 11 insertions(+)