From patchwork Tue Mar 29 12:24:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyrille Pitchen X-Patchwork-Id: 602873 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qZ92F0mYdz9s0M for ; Tue, 29 Mar 2016 23:24:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757212AbcC2MYR (ORCPT ); Tue, 29 Mar 2016 08:24:17 -0400 Received: from eusmtp01.atmel.com ([212.144.249.242]:24105 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757158AbcC2MYP (ORCPT ); Tue, 29 Mar 2016 08:24:15 -0400 Received: from tenerife.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.30) with Microsoft SMTP Server id 14.3.235.1; Tue, 29 Mar 2016 14:24:04 +0200 From: Cyrille Pitchen To: , CC: , , , , , , , , , , Cyrille Pitchen Subject: [PATCH v4 2/2] doc: dt: mtd: add a DT property to enable the use of 4byte-address op codes Date: Tue, 29 Mar 2016 14:24:13 +0200 Message-ID: <320899457d15b85eb0b71edd566cae035d7e1f55.1459251929.git.cyrille.pitchen@atmel.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds a new optional DT property which enables an alternative way of supporting memory size above 16MiB (128Mib). This new mechanism translates the regular 3byte-address op codes into their 4byte-address version whereas the old/default mecanism makes the SPI memory enter its 4byte-address mode, which has annoying side effects for early bootloaders. We cannot discover at run time whether the SPI NOR memory supports the 4byte-address op codes. For instance both Macronix MX25L25635E and MX25L25673G share the same JEDEC ID (C22019 without any extension byte). However the first one doesn't support 4byte-address op codes whereas the second one does. Signed-off-by: Cyrille Pitchen Acked-by: Rob Herring --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 2c91c03e7eb0..3cf1b3cdafe8 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -66,6 +66,17 @@ Optional properties: Refer to your chips' datasheet to check if this is supported by your chip. +- spi-nor-4byte-opcodes: For memory size above 16MiB (128Mib), use the dedicated + 4byte-address opcodes instead of entering the 4byte + address mode. This mode changes the internal state of + the chip so may conflict with some early boot loaders, + which expect to use the regular (Fast) Read opcodes + with 3byte address. + However 4byte-address opcodes are not supported by all + chips and support for them cannot be detected at + runtime. Refer to you chip's datasheet to check if this + is supported by your chip. + Example: flash: m25p80@0 {