| Message ID | 20230616170022.76107-4-sebastian.reichel@collabora.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | RK3588 PCIe2 support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Fri, 16 Jun 2023 19:00:21 +0200, Sebastian Reichel wrote: > The PCIe 2.0 controllers on RK3588 need one additional clock, > one additional reset line and one for ranges entry. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > .../bindings/pci/rockchip-dw-pcie.yaml | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Fri, Jun 16, 2023 at 07:00:21PM +0200, Sebastian Reichel wrote: > The PCIe 2.0 controllers on RK3588 need one additional clock, > one additional reset line and one for ranges entry. Just a nitpick: it would be perfect to have these new items evaluated compatible-string conditionally. Anyway: Reviewed-by: Serge Semin <fancer.lancer@gmail.com> -Serge(y) > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > .../bindings/pci/rockchip-dw-pcie.yaml | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > index bf81d306cc80..7897af0ec297 100644 > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > @@ -41,20 +41,24 @@ properties: > - const: config > > clocks: > + minItems: 5 > items: > - description: AHB clock for PCIe master > - description: AHB clock for PCIe slave > - description: AHB clock for PCIe dbi > - description: APB clock for PCIe > - description: Auxiliary clock for PCIe > + - description: PIPE clock > > clock-names: > + minItems: 5 > items: > - const: aclk_mst > - const: aclk_slv > - const: aclk_dbi > - const: pclk > - const: aux > + - const: pipe > > interrupts: > maxItems: 5 > @@ -97,13 +101,19 @@ properties: > maxItems: 1 > > ranges: > - maxItems: 2 > + minItems: 2 > + maxItems: 3 > > resets: > - maxItems: 1 > + minItems: 1 > + maxItems: 2 > > reset-names: > - const: pipe > + oneOf: > + - const: pipe > + - items: > + - const: pwr > + - const: pipe > > vpcie3v3-supply: true > > -- > 2.39.2 >
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index bf81d306cc80..7897af0ec297 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -41,20 +41,24 @@ properties: - const: config clocks: + minItems: 5 items: - description: AHB clock for PCIe master - description: AHB clock for PCIe slave - description: AHB clock for PCIe dbi - description: APB clock for PCIe - description: Auxiliary clock for PCIe + - description: PIPE clock clock-names: + minItems: 5 items: - const: aclk_mst - const: aclk_slv - const: aclk_dbi - const: pclk - const: aux + - const: pipe interrupts: maxItems: 5 @@ -97,13 +101,19 @@ properties: maxItems: 1 ranges: - maxItems: 2 + minItems: 2 + maxItems: 3 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: - const: pipe + oneOf: + - const: pipe + - items: + - const: pwr + - const: pipe vpcie3v3-supply: true
The PCIe 2.0 controllers on RK3588 need one additional clock, one additional reset line and one for ranges entry. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> --- .../bindings/pci/rockchip-dw-pcie.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)