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[RFC,00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC

Message ID 20231226053848.25089-1-jeeheng.sia@starfivetech.com
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Series Basic clock and reset support for StarFive JH8100 RISC-V SoC | expand

Message

JeeHeng Sia Dec. 26, 2023, 5:38 a.m. UTC 
This patch series enabled basic clock & reset support for StarFive
JH8100 SoC.

This patch series depends on the Initial device tree support for
StarFive JH8100 SoC patch series which can be found at [1].

As it is recommended to refrain from merging fundamental patches like
Device Tree, Clock & Reset, and PINCTRL tested on FPGA/Emulator, into the
RISC-V Mainline, this patch series has been renamed to "RFC" patches. Yet,
thanks to the reviewers who have reviewed the patches at [2]. The changes
are captured below.

StarFive JH8100 shares a similar clock and reset design with JH7110.
To facilitate the reuse of the file and its functionalities, files
containing the 'jh71x0' naming convention are renamed to use the
'common' wording. Internal functions that contain the 'jh71x0'
naming convention are renamed to use 'starfive.' This is accomplished
through patches 1, 2, 3, and 4.

Patch 5 adds documentation to describe System (SYSCRG) Clock & Reset
binding.
Patch 6 adds SYSCRG clock driver.

patch 7 adds documentation to describe North-West (NWCRG) Clock & Reset
binding.
Patch 8 adds NWCRG clock driver.

patch 9 adds documentation to describe North-East (NECRG) Clock & Reset
binding.
Patch 10 adds NECRG clock driver.

patch 11 adds documentation to describe South-West (SWCRG) Clock & Reset
binding.
Patch 12 adds SWCRG clock driver.

patch 13 adds documentation to describe Always-On (AON) Clock & Reset
binding.
Patch 14 adds AON clock driver.

Patch 15 adds support for the auxiliary reset driver.

Patch 16 adds clocks and reset nodes to the JH8100 device tree.

Changes since [2]:
- Renamed the patch series to "RFC" patches.
- Added the "Reviewed-by" tag from Emil for patches 1, 2 3 & 4.
- Removed clk_ prefixes.
- Used 4 spaces for example indentation in dt-binding documentation.
- Used the same license in dt-binding.
- Moved number of clocks from binding to source file.
- Moved number of resets from binding ro source file.
- Removed the subfolder for new clock files.
- Followed the JH71xx files naming convention.
- Followed the JH71xx clock naming conventions.
- Followed the JH71xx resets naming conventions.
- Moved the PLL fixed clock from the source file to Device Tree.
- Dropped clk.dtsi and moved the clocks node to SoC.dtsi.

[1] https://lore.kernel.org/lkml/20231201121410.95298-1-jeeheng.sia@starfivetech.com/
[2] https://lore.kernel.org/lkml/20231206115000.295825-1-jeeheng.sia@starfivetech.com/

Sia Jee Heng (16):
  reset: starfive: Rename file name "jh71x0" to "common"
  reset: starfive: Convert the word "jh71x0" to "starfive"
  clk: starfive: Rename file name "jh71x0" to "common"
  clk: starfive: Convert the word "jh71x0" to "starfive"
  dt-bindings: clock: Add StarFive JH8100 System clock and reset
    generator
  clk: starfive: Add JH8100 System clock generator driver
  dt-bindings: clock: Add StarFive JH8100 North-West clock and reset
    generator
  clk: starfive: Add JH8100 North-West clock generator driver
  dt-bindings: clock: Add StarFive JH8100 North-East clock and reset
    generator
  clk: starfive: Add JH8100 North-East clock generator driver
  dt-bindings: clock: Add StarFive JH8100 South-West clock and reset
    generator
  clk: starfive: Add JH8100 South-West clock generator driver
  dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset
    generator
  clk: starfive: Add JH8100 Always-On clock generator driver
  reset: starfive: Add StarFive JH8100 reset driver
  riscv: dts: starfive: jh8100: Add clocks and resets nodes

 .../clock/starfive,jh8100-aoncrg.yaml         |  74 +++
 .../bindings/clock/starfive,jh8100-necrg.yaml | 153 +++++
 .../bindings/clock/starfive,jh8100-nwcrg.yaml | 119 ++++
 .../bindings/clock/starfive,jh8100-swcrg.yaml |  64 +++
 .../clock/starfive,jh8100-syscrg.yaml         |  77 +++
 MAINTAINERS                                   |  15 +
 arch/riscv/boot/dts/starfive/jh8100.dtsi      | 313 +++++++++++
 drivers/clk/starfive/Kconfig                  |  45 +-
 drivers/clk/starfive/Makefile                 |   8 +-
 drivers/clk/starfive/clk-starfive-common.c    | 327 +++++++++++
 drivers/clk/starfive/clk-starfive-common.h    | 130 +++++
 .../clk/starfive/clk-starfive-jh7100-audio.c  | 127 ++---
 drivers/clk/starfive/clk-starfive-jh7100.c    | 503 ++++++++---------
 .../clk/starfive/clk-starfive-jh7110-aon.c    |  62 +--
 .../clk/starfive/clk-starfive-jh7110-isp.c    |  72 +--
 .../clk/starfive/clk-starfive-jh7110-stg.c    |  94 ++--
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 523 +++++++++---------
 .../clk/starfive/clk-starfive-jh7110-vout.c   |  74 +--
 drivers/clk/starfive/clk-starfive-jh7110.h    |   4 +-
 drivers/clk/starfive/clk-starfive-jh71x0.c    | 327 -----------
 drivers/clk/starfive/clk-starfive-jh71x0.h    | 123 ----
 .../clk/starfive/clk-starfive-jh8100-aon.c    | 256 +++++++++
 drivers/clk/starfive/clk-starfive-jh8100-ne.c | 499 +++++++++++++++++
 drivers/clk/starfive/clk-starfive-jh8100-nw.c | 237 ++++++++
 drivers/clk/starfive/clk-starfive-jh8100-sw.c | 134 +++++
 .../clk/starfive/clk-starfive-jh8100-sys.c    | 415 ++++++++++++++
 drivers/clk/starfive/clk-starfive-jh8100.h    |  11 +
 drivers/reset/starfive/Kconfig                |  14 +-
 drivers/reset/starfive/Makefile               |   4 +-
 ...rfive-jh71x0.c => reset-starfive-common.c} |  68 +--
 .../reset/starfive/reset-starfive-common.h    |  14 +
 .../reset/starfive/reset-starfive-jh7100.c    |   4 +-
 .../reset/starfive/reset-starfive-jh7110.c    |   8 +-
 .../reset/starfive/reset-starfive-jh71x0.h    |  14 -
 .../reset/starfive/reset-starfive-jh8100.c    | 108 ++++
 .../dt-bindings/clock/starfive,jh8100-crg.h   | 421 ++++++++++++++
 .../dt-bindings/reset/starfive,jh8100-crg.h   | 118 ++++
 ...rfive-jh71x0.h => reset-starfive-common.h} |  10 +-
 38 files changed, 4327 insertions(+), 1242 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml
 create mode 100644 drivers/clk/starfive/clk-starfive-common.c
 create mode 100644 drivers/clk/starfive/clk-starfive-common.h
 delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
 delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
 create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-aon.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-ne.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-nw.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-sw.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-sys.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh8100.h
 rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (55%)
 create mode 100644 drivers/reset/starfive/reset-starfive-common.h
 delete mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
 create mode 100644 drivers/reset/starfive/reset-starfive-jh8100.c
 create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h
 create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h
 rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (50%)

Comments

Krzysztof Kozlowski Dec. 26, 2023, 1:33 p.m. UTC | #1 
On 26/12/2023 06:38, Sia Jee Heng wrote:
> 
> Patch 16 adds clocks and reset nodes to the JH8100 device tree.
> 
> Changes since [2]:

Then this is v2, please version your patches correctly, so tools and
people will understand it.

Best regards,
Krzysztof
Krzysztof Kozlowski Dec. 26, 2023, 1:38 p.m. UTC | #2 
On 26/12/2023 06:38, Sia Jee Heng wrote:
> Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> nodes for JH8100 RISC-V SoC.
> 
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> ---

...

>  		compatible = "simple-bus";
>  		interrupt-parent = <&plic>;
> @@ -357,6 +563,99 @@ uart4: serial@121a0000  {
>  			status = "disabled";
>  		};
>  
> +		necrg: necrg@12320000 {

This is a friendly reminder during the review process.

It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.

Thank you.

Best regards,
Krzysztof
JeeHeng Sia Dec. 27, 2023, 11:02 a.m. UTC | #3 
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, December 26, 2023 9:39 PM
> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; conor@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu;
> mturquette@baylibre.com; sboyd@kernel.org; p.zabel@pengutronix.de; emil.renner.berthing@canonical.com; Hal Feng
> <hal.feng@starfivetech.com>; Xingyu Wu <xingyu.wu@starfivetech.com>
> Cc: linux-riscv@lists.infradead.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org; Leyfoon Tan
> <leyfoon.tan@starfivetech.com>
> Subject: Re: [RFC 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
> 
> On 26/12/2023 06:38, Sia Jee Heng wrote:
> > Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> > nodes for JH8100 RISC-V SoC.
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > ---
> 
> ...
> 
> >  		compatible = "simple-bus";
> >  		interrupt-parent = <&plic>;
> > @@ -357,6 +563,99 @@ uart4: serial@121a0000  {
> >  			status = "disabled";
> >  		};
> >
> > +		necrg: necrg@12320000 {
> 
> This is a friendly reminder during the review process.
Thank you for the friendly reminder and your valuable feedback.
I appreciate your guidance during the review process.
Your input is crucial, and I'm committed to delivering high-quality code.
Thanks again for your time and feedback. 
> 
> It seems my or other reviewer's previous comments were not fully
> addressed. Maybe the feedback got lost between the quotes, maybe you
> just forgot to apply it. Please go back to the previous discussion and
> either implement all requested changes or keep discussing them.
I didn't ignore your comment. Instead, I misinterpreted it as suggesting
the use of a dash instead of an underscore for the node's name. I will make
the necessary adjustment and change it back to 'clock-controller'.
> 
> Thank you.
> 
> Best regards,
> Krzysztof
JeeHeng Sia Dec. 27, 2023, 11:03 a.m. UTC | #4 
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, December 26, 2023 9:33 PM
> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; conor@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu;
> mturquette@baylibre.com; sboyd@kernel.org; p.zabel@pengutronix.de; emil.renner.berthing@canonical.com; Hal Feng
> <hal.feng@starfivetech.com>; Xingyu Wu <xingyu.wu@starfivetech.com>
> Cc: linux-riscv@lists.infradead.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org; Leyfoon Tan
> <leyfoon.tan@starfivetech.com>
> Subject: Re: [RFC 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC
> 
> On 26/12/2023 06:38, Sia Jee Heng wrote:
> >
> > Patch 16 adds clocks and reset nodes to the JH8100 device tree.
> >
> > Changes since [2]:
> 
> Then this is v2, please version your patches correctly, so tools and
> people will understand it.
Noted. Will get it fixed in the next version.
> 
> Best regards,
> Krzysztof