From patchwork Tue Dec 26 05:38:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 1880183 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-28435-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SzkCJ2r5Jz20RL for ; Tue, 26 Dec 2023 16:41:00 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 8D8F8280D57 for ; Tue, 26 Dec 2023 05:40:58 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3C0DC4C632; Tue, 26 Dec 2023 05:39:47 +0000 (UTC) X-Original-To: devicetree@vger.kernel.org Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CED24C63C; Tue, 26 Dec 2023 05:39:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 70A838022; Tue, 26 Dec 2023 13:39:36 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:36 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:30 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator Date: Tue, 26 Dec 2023 13:38:37 +0800 Message-ID: <20231226053848.25089-6-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the System clocks and reset generator (SYSCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Reviewed-by: Krzysztof Kozlowski --- .../clock/starfive,jh8100-syscrg.yaml | 77 +++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 122 ++++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 21 +++ 3 files changed, 220 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml new file mode 100644 index 000000000000..853b13ce5562 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 System Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-syscrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: External MCLK clock + - description: PLL0 + - description: PLL1 + - description: PLL2 + - description: PLL3 + - description: PLL4 + - description: PLL6 + - description: PLL7 + + clock-names: + items: + - const: osc + - const: mclk-ext + - const: pll0 + - const: pll1 + - const: pll2 + - const: pll3 + - const: pll4 + - const: pll6 + - const: pll7 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@126d0000 { + compatible = "starfive,jh8100-syscrg"; + reg = <0x126d0000 0x10000>; + clocks = <&osc>, <&mclk_ext>, <&pll0>, <&pll1>, + <&pll2>, <&pll3>, <&pll4>, <&pll6>, <&pll7>; + clock-names = "osc", "mclk-ext", "pll0", "pll1", + "pll2", "pll3", "pll4", + "pll6", "pll7"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h new file mode 100644 index 000000000000..611613961e17 --- /dev/null +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Sia Jee Heng + * + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ + +/* SYSCRG clocks */ +#define JH8100_SYSCLK_VDEC_ROOT_PREOSC 0 +#define JH8100_SYSCLK_VDEC_ROOT 1 +#define JH8100_SYSCLK_VENC_ROOT_PREOSC 2 +#define JH8100_SYSCLK_VENC_ROOT 3 +#define JH8100_SYSCLK_GPU_ROOT 4 +#define JH8100_SYSCLK_GPU_CORE 5 +#define JH8100_SYSCLK_VOUT_ROOT0_PREOSC 6 +#define JH8100_SYSCLK_VOUT_ROOT0 7 +#define JH8100_SYSCLK_VOUT_ROOT1_PREOSC 8 +#define JH8100_SYSCLK_VOUT_ROOT1 9 +#define JH8100_SYSCLK_VOUT_SCAN_ATS 10 +#define JH8100_SYSCLK_PERH_ROOT_PREOSC 11 +#define JH8100_SYSCLK_PERH_ROOT 12 +#define JH8100_SYSCLK_AXI_200_PREOSC 13 +#define JH8100_SYSCLK_AXI_200 14 +#define JH8100_SYSCLK_AXI_200_GMAC 15 +#define JH8100_SYSCLK_AXI_500_PREOSC 16 +#define JH8100_SYSCLK_AXI_500 17 +#define JH8100_SYSCLK_AXI_500_PCIEX1A 18 +#define JH8100_SYSCLK_AXI_500_PCIEX1B 19 +#define JH8100_SYSCLK_AXI_500_PCIEX2 20 +#define JH8100_SYSCLK_AXI_500_PCIEX8 21 +#define JH8100_SYSCLK_AXI_400_PREOSC 22 +#define JH8100_SYSCLK_AXI_400 23 +#define JH8100_SYSCLK_AXI_400_APBOOTRAM 24 +#define JH8100_SYSCLK_AXI_125_PREOSC 25 +#define JH8100_SYSCLK_AXI_125 26 +#define JH8100_SYSCLK_AHB0_PREOSC 27 +#define JH8100_SYSCLK_AHB0 28 +#define JH8100_SYSCLK_APB_BUS_FUNC 29 +#define JH8100_SYSCLK_APB_BUS 30 +#define JH8100_SYSCLK_APB_BUS_PER0 31 +#define JH8100_SYSCLK_APB_BUS_PER1 32 +#define JH8100_SYSCLK_APB_BUS_PER2 33 +#define JH8100_SYSCLK_APB_BUS_PER3 34 +#define JH8100_SYSCLK_APB_BUS_PER4 35 +#define JH8100_SYSCLK_APB_BUS_PER5 36 +#define JH8100_SYSCLK_APB_BUS_PER6 37 +#define JH8100_SYSCLK_APB_BUS_PER7 38 +#define JH8100_SYSCLK_APB_BUS_PER8 39 +#define JH8100_SYSCLK_APB_BUS_PER9 40 +#define JH8100_SYSCLK_APB_BUS_PER10 41 +#define JH8100_SYSCLK_SPI_CORE_100 42 +#define JH8100_SYSCLK_PLL1_DIV2 43 +#define JH8100_SYSCLK_PLL2_DIV2 44 +#define JH8100_SYSCLK_PLL3_DIV2 45 +#define JH8100_SYSCLK_PLL4_DIV2 46 +#define JH8100_SYSCLK_PLL6_DIV2 47 +#define JH8100_SYSCLK_PLL7_DIV2 48 +#define JH8100_SYSCLK_AUDIO_ROOT 49 +#define JH8100_SYSCLK_MCLK_INNER 50 +#define JH8100_SYSCLK_MCLK 51 +#define JH8100_SYSCLK_MCLK_OUT 52 +#define JH8100_SYSCLK_ISP_2X_PREOSC 53 +#define JH8100_SYSCLK_ISP_2X 54 +#define JH8100_SYSCLK_ISP_AXI 55 +#define JH8100_SYSCLK_GCLK1 56 +#define JH8100_SYSCLK_GCLK2 57 +#define JH8100_SYSCLK_GCLK3 58 +#define JH8100_SYSCLK_GCLK4 59 +#define JH8100_SYSCLK_GCLK6 60 +#define JH8100_SYSCLK_GCLK7 61 +#define JH8100_SYSCLK_FLEXNOC0_PREOSC 62 +#define JH8100_SYSCLK_FLEXNOC0 63 +#define JH8100_SYSCLK_FLEXNOC1_PREOSC 64 +#define JH8100_SYSCLK_FLEXNOC1 65 +#define JH8100_SYSCLK_FLEXNOC2_PREOSC 66 +#define JH8100_SYSCLK_FLEXNOC2 67 +#define JH8100_SYSCLK_VDEC_CORE 68 +#define JH8100_SYSCLK_GPU_CORE_ICG 69 +#define JH8100_SYSCLK_IMG_GPU_CLK_APB 70 +#define JH8100_SYSCLK_IMG_GPU_RTC_TOGGLE 71 +#define JH8100_SYSCLK_IMG_GPU_TIMER_USC 72 +#define JH8100_SYSCLK_HIFI4_CORE_PREOSC 73 +#define JH8100_SYSCLK_HIFI4_CORE 74 +#define JH8100_SYSCLK_E_200_PREOSC 75 +#define JH8100_SYSCLK_E_200 76 +#define JH8100_SYSCLK_HD_AUDIO_48M 77 +#define JH8100_SYSCLK_VOUT_DC_CORE 78 +#define JH8100_SYSCLK_VOUT_AXI 79 +#define JH8100_SYSCLK_USB_WRAP_625 80 +#define JH8100_SYSCLK_USB_WRAP_480 81 +#define JH8100_SYSCLK_USB_WRAP_240 82 +#define JH8100_SYSCLK_USB_WRAP_60 83 +#define JH8100_SYSCLK_USB_WRAP_156P25 84 +#define JH8100_SYSCLK_USB_WRAP_312P5 85 +#define JH8100_SYSCLK_USB_125M 86 +#define JH8100_SYSCLK_FLEXNOC_APBOOTRAM 87 +#define JH8100_SYSCLK_FLEXNOC_PCIEX1AMST 88 +#define JH8100_SYSCLK_FLEXNOC_PCIEX1ASLV 89 +#define JH8100_SYSCLK_FLEXNOC_PCIEX1BMST 90 +#define JH8100_SYSCLK_FLEXNOC_PCIEX1BSLV 91 +#define JH8100_SYSCLK_FLEXNOC_PCIEX2MST 92 +#define JH8100_SYSCLK_FLEXNOC_PCIEX2SLV 93 +#define JH8100_SYSCLK_FLEXNOC_PCIEX8MST 94 +#define JH8100_SYSCLK_FLEXNOC_PCIEX8SLV 95 +#define JH8100_SYSCLK_FLEXNOC_GMACSYSSLV 96 +#define JH8100_SYSCLK_GMAC_SRC 97 +#define JH8100_SYSCLK_GMAC1_GTXCLK_TOP 98 +#define JH8100_SYSCLK_GMAC1_PTP 99 +#define JH8100_SYSCLK_HD_AUDIO_SYSTEM_CLOCK 100 +#define JH8100_SYSCLK_HD_AUDIO_CLOCK_48 101 +#define JH8100_SYSCLK_HD_AUDIO_BCLK_POST_OCC_IN 102 +#define JH8100_SYSCLK_NNE_VIP_ACLK 103 +#define JH8100_SYSCLK_NNE_VIP_HCLK 104 +#define JH8100_SYSCLK_NNE_VIP_CLKCORE 105 +#define JH8100_SYSCLK_GPU_ICG_EN 106 +#define JH8100_SYSCLK_HD_AUDIO_ICG_EN 107 +#define JH8100_SYSCLK_NNE_ICG_EN 108 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h new file mode 100644 index 000000000000..c4e2501491ab --- /dev/null +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) 2022-2023 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ + +/* + * SYSCRG resets: assert0 + */ +#define JH8100_SYSRST_SYS_SYSCON 0 +#define JH8100_SYSRST_CLK_MOD 1 +#define JH8100_SYSRST_GPU 2 +#define JH8100_SYSRST_GPU_SPU 3 +#define JH8100_SYSRST_GPU_TVSENSOR 4 +#define JH8100_SYSRST_PPU_OP_NORET_GPU_RESET 5 +#define JH8100_SYSRST_NNE 6 +#define JH8100_SYSRST_HD_AUDIO 7 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 1880184 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=devicetree+bounces-28437-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SzkCy4T0Qz20RL for ; Tue, 26 Dec 2023 16:41:34 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 61D3028116F for ; Tue, 26 Dec 2023 05:41:33 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 892504BAA0; Tue, 26 Dec 2023 05:39:54 +0000 (UTC) X-Original-To: devicetree@vger.kernel.org Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B9924D10C; Tue, 26 Dec 2023 05:39:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 6B9658016; Tue, 26 Dec 2023 13:39:49 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:49 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:43 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 07/16] dt-bindings: clock: Add StarFive JH8100 North-West clock and reset generator Date: Tue, 26 Dec 2023 13:38:39 +0800 Message-ID: <20231226053848.25089-8-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the North-West clock and reset generator (NWCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/starfive,jh8100-nwcrg.yaml | 119 ++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 43 +++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 14 +++ 3 files changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml new file mode 100644 index 000000000000..be0f94e64e6a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-nwcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 North-West Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-nwcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: APB_BUS clock from SYSCRG + - description: APB_BUS_PER4 clock from SYSCRG + - description: SPI_CORE_100 clock from SYSCRG + - description: ISP_2X clock from SYSCRG + - description: ISP_AXI clock from SYSCRG + - description: VOUT_ROOT0 clock from SYSCRG + - description: VOUT_ROOT1 clock from SYSCRG + - description: VOUT_SCAN_ATS clock from SYSCRG + - description: VOUT_DC_CORE clock from SYSCRG + - description: VOUT_AXI clock from SYSCRG + - description: AXI_400 clock from SYSCRG + - description: AHB0 clock from SYSCRG + - description: PERH_ROOT_PREOSC from SYSCRG + - description: External DVP clock + - description: External ISP DPHY TAP TCK clock + - description: External golbal clock + - description: External VOUT MIPI DPHY TAP TCK + - description: External VOUT eDP TAP TCK + - description: External SPI In2 clock + - description: PLL5 + + clock-names: + items: + - const: osc + - const: apb_bus + - const: apb_bus_per4 + - const: spi_core_100 + - const: isp_2x + - const: isp_axi + - const: vout_root0 + - const: vout_root1 + - const: vout_scan_ats + - const: vout_dc_core + - const: vout_axi + - const: axi_400 + - const: ahb0 + - const: perh_root_preosc + - const: dvp-ext + - const: isp-dphy-tap-tck-ext + - const: glb-ext-clk + - const: vout-mipi-dphy-tap-tck-ext + - const: vout-edp-tap-tck-ext + - const: spi-in2-ext + - const: pll5 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@123c0000 { + compatible = "starfive,jh8100-nwcrg"; + reg = <0x123c0000 0x10000>; + clocks = <&osc>, <&syscrg JH8100_SYSCLK_APB_BUS>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER4>, + <&syscrh JH8100_SYSCLK_SPI_CORE_100>, + <&syscrg JH8100_SYSCLK_ISP_2X>, + <&syscrg JH8100_SYSCLK_ISP_AXI>, + <&syscrg JH8100_SYSCLK_VOUT_ROOT0>, + <&syscrg JH8100_SYSCLK_VOUT_ROOT1>, + <&syscrg JH8100_SYSCLK_VOUT_SCAN_ATS>, + <&syscrg JH8100_SYSCLK_VOUT_DC_CORE>, + <&syscrg JH8100_SYSCLK_VOUT_AXI>, + <&syscrg JH8100_SYSCLK_AXI_400>, + <&syscrg JH8100_SYSCLK_AHB0>, + <&syscrg JH8100_SYSCLK_PERH_ROOT_PREOSC>, + <&dvp_ext>, <&isp_dphy_tap_tck_ext>, + <&glb_ext_clk>, <&vout_mipi_dphy_tap_tck_ext>, + <&vout_edp_tap_tck_ext>, <&spi_in2_ext>, <&pll5>; + clock-names = "osc", "apb_bus", "apb_bus_per4", "spi_core_100", + "isp_2x", "isp_axi", "vout_root0", "vout_root1", + "vout_scan_ats", "vout_dc_core", "vout_axi", + "axi_400", "ahb0", "perh_root_preosc", "dvp-ext", + "isp-dphy-tap-tck-ext", "glb-ext-clk", + "vout-mipi-dphy-tap-tck-ext", "vout-edp-tap-tck-ext", + "spi-in2-ext", "pll5"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index 611613961e17..626173e14940 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -119,4 +119,47 @@ #define JH8100_SYSCLK_HD_AUDIO_ICG_EN 107 #define JH8100_SYSCLK_NNE_ICG_EN 108 +/* NWCRG clocks */ +#define JH8100_NWCLK_PLL5_DIV2 0 +#define JH8100_NWCLK_GCLK5 1 +#define JH8100_NWCLK_GPIO_100 2 +#define JH8100_NWCLK_GPIO_50 3 +#define JH8100_NWCLK_GPIO_150 4 +#define JH8100_NWCLK_GPIO_60 5 +#define JH8100_NWCLK_IOMUX_WEST_PCLK 6 +#define JH8100_NWCLK_I2C6_APB 7 +#define JH8100_NWCLK_I2C7_APB 8 +#define JH8100_NWCLK_SPI2_APB 9 +#define JH8100_NWCLK_SPI2_CORE 10 +#define JH8100_NWCLK_SPI2_SCLK_IN 11 +#define JH8100_NWCLK_SMBUS1_APB 12 +#define JH8100_NWCLK_SMBUS1_CORE 13 +#define JH8100_NWCLK_ISP_DVP 14 +#define JH8100_NWCLK_ISP_CORE_2X 15 +#define JH8100_NWCLK_ISP_AXI 16 +#define JH8100_NWCLK_ISP_DPHY_TAP_TCK 17 +#define JH8100_NWCLK_FLEXNOC_ISPSLV 18 +#define JH8100_NWCLK_VOUT_PIX0 19 +#define JH8100_NWCLK_VOUT_PIX1 20 +#define JH8100_NWCLK_VOUT_SCAN_ATS 21 +#define JH8100_NWCLK_VOUT_DC_CORE 22 +#define JH8100_NWCLK_VOUT_APB 23 +#define JH8100_NWCLK_VOUT_DSI 24 +#define JH8100_NWCLK_VOUT_AHB 25 +#define JH8100_NWCLK_VOUT_AXI 26 +#define JH8100_NWCLK_VOUT_MIPI_DPHY_TAP_TCK 27 +#define JH8100_NWCLK_VOUT_EDP_PHY_TAP_TCK 28 +#define JH8100_NWCLK_UART5_CORE_PREOSC 29 +#define JH8100_NWCLK_UART5_APB 30 +#define JH8100_NWCLK_UART5_CORE 31 +#define JH8100_NWCLK_UART6_CORE_PREOSC 32 +#define JH8100_NWCLK_UART6_APB 33 +#define JH8100_NWCLK_UART6_CORE 34 +#define JH8100_NWCLK_SPI2_ICG_EN 35 +#define JH8100_NWCLK_SMBUS1_ICG_EN 36 +#define JH8100_NWCLK_ISP_ICG_EN 37 +#define JH8100_NWCLK_VOUT_ICG_EN 38 +#define JH8100_NWCLK_UART5_ICG_EN 39 +#define JH8100_NWCLK_UART6_ICG_EN 40 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index c4e2501491ab..b25f6522f3d4 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -18,4 +18,18 @@ #define JH8100_SYSRST_NNE 6 #define JH8100_SYSRST_HD_AUDIO 7 +/* + * NWCRG resets: assert0 + */ +#define JH8100_NWRST_PRESETN 0 +#define JH8100_NWRST_SYS_IOMUX_W 1 +#define JH8100_NWRST_I2C6 2 +#define JH8100_NWRST_I2C7 3 +#define JH8100_NWRST_SPI2 4 +#define JH8100_NWRST_SMBUS1 5 +#define JH8100_NWRST_UART5 6 +#define JH8100_NWRST_UART6 7 +#define JH8100_NWRST_MERAK0_TVSENSOR 8 +#define JH8100_NWRST_MERAK1_TVSENSOR 9 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:41 2023 Content-Type: text/plain; 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Tue, 26 Dec 2023 13:40:02 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:56 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 09/16] dt-bindings: clock: Add StarFive JH8100 North-East clock and reset generator Date: Tue, 26 Dec 2023 13:38:41 +0800 Message-ID: <20231226053848.25089-10-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the North-East clock and reset generator (NECRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/starfive,jh8100-necrg.yaml | 153 +++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 177 ++++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 59 ++++++ 3 files changed, 389 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml new file mode 100644 index 000000000000..f747b85fa457 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-necrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 North-East Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-necrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: AXI_400 clock from SYSCRG + - description: VOUT_ROOT0 clock from SYSCRG + - description: VOUT_ROOT1 clock from SYSCRG + - description: USB_WRAP_480 clock from SYSCRG + - description: USB_WRAP_625 clock from SYSCRG + - description: USB_WRAP_240 clock from SYSCRG + - description: USB_WRAP_60 clock from SYSCRG + - description: USB_WRAP_156P25 clock from SYSCRG + - description: USB_WRAP_312P5 clock from SYSCRG + - description: USB_125M clock from SYSCRG + - description: GPIO_100 clock from NWCRG + - description: PERH_ROOT clock from SYSCRG + - description: Master clock from SYSCRG + - description: PERH_ROOT_PREOSC clock from SYSCRG + - description: AHB0 clock from SYSCRG + - description: APB_BUS_PER1 clock from SYSCRG + - description: APB_BUS PER2 clock from SYSCRG + - description: APB_BUS_PER3 clock from SYSCRG + - description: APB_BUS_PER5 clock from SYSCRG + - description: VENC_ROOT clock from SYSCRG + - description: SPI_CORE_100 clock from SYSCRG + - description: External global clock + - description: External USB3_TAP_TCK clock + - description: External USB1_TAP_TCK clock + - description: External USB2_TAP_TCK clock + - description: External TYPEC_TAP_TCK clock + - description: External SPI_IN0 clock + - description: External SPI_IN1 clock + - description: External I2STX_BCLK clock + - description: External I2STX_LRCK clock + + clock-names: + items: + - const: osc + - const: axi_400 + - const: vout_root0 + - const: vout_root1 + - const: usb_wrap_480 + - const: usb_wrap_625 + - const: usb_wrap_240 + - const: usb_wrap_60 + - const: usb_wrap_156p25 + - const: usb_wrap_312p5 + - const: usb_125m + - const: gpio_100 + - const: perh_root + - const: mclk + - const: perh_root_preosc + - const: ahb0 + - const: apb_bus_per1 + - const: apb_bus_per2 + - const: apb_bus_per3 + - const: apb_bus_per5 + - const: venc_root + - const: spi_core_100 + - const: glb-ext-clk + - const: usb3-tap-tck-ext + - const: usb1-tap-tck-ext + - const: usb2-tap-tck-ext + - const: typec-tap-tck-ext + - const: spi-in0-ext + - const: spi-in1-ext + - const: i2stx-bclk-ext + - const: i2stx-lrck-ext + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@12320000 { + compatible = "starfive,jh8100-necrg"; + reg = <0x12320000 0x10000>; + clocks = <&osc>, <&syscrg JH8100_SYSCLK_AXI_400>, + <&syscrg JH8100_SYSCLK_VOUT_ROOT0>, + <&syscrg JH8100_SYSCLK_VOUT_ROOT1>, + <&syscrg JH8100_SYSCLK_USB_WRAP_480>, + <&syscrg JH8100_SYSCLK_USB_WRAP_625>, + <&syscrg JH8100_SYSCLK_USB_WRAP_240>, + <&syscrg JH8100_SYSCLK_USB_WRAP_60>, + <&syscrg JH8100_SYSCLK_USB_WRAP_156P25>, + <&syscrg JH8100_SYSCLK_USB_WRAP_312P5>, + <&syscrg JH8100_SYSCLK_USB_125M>, + <&nwcrg JH8100_NWCLK_GPIO_100>, + <&syscrg JH8100_SYSCLK_PERH_ROOT>, + <&syscrg JH8100_SYSCLK_MCLK>, + <&syscrg JH8100_SYSCLK_PERH_ROOT_PREOSC>, + <&syscrg JH8100_SYSCLK_AHB0>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER1>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER2>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER3>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER5>, + <&syscrg JH8100_SYSCLK_VENC_ROOT>, + <&syscrg JH8100_SYSCLK_SPI_CORE_100>, + <&glb_ext_clk>, <&usb3_tap_tck_ext>, + <&usb1_tap_tck_ext>, <&usb2_tap_tck_ext>, + <&typec_tap_tck_ext>, <&spi_in0_ext>, + <&spi_in1_ext>, <&i2stx_bclk_ext>, + <&i2stx_lrck_ext>; + clock-names = "osc", "axi_400", "vout_root0", "vout_root1", + "usb_wrap_480", "usb_wrap_625", "usb_wrap_240", + "usb_wrap_60", "usb_wrap_156p25", "usb_wrap_312p5", + "usb_125m", "gpio_100", "perh_root", "mclk", + "perh_root_preosc", "ahb0", "apb_bus_per1", + "apb_bus_per2", "apb_bus_per3", "apb_bus_per5", + "venc_root", "spi_core_100", "glb-ext-clk", + "usb3-tap-tck-ext", "usb1-tap-tck-ext", + "usb2-tap-tck-ext", "typec-tap-tck-ext", + "spi-in0-ext", "spi-in1-ext", "i2stx-bclk-ext", + "i2stx-lrck-ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index 626173e14940..c37b42f3eacd 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -162,4 +162,181 @@ #define JH8100_NWCLK_UART5_ICG_EN 39 #define JH8100_NWCLK_UART6_ICG_EN 40 +/* NECRG clocks */ +#define JH8100_NECLK_FLEXNOC_DMASLV 0 +#define JH8100_NECLK_MAILBOX_APB 1 +#define JH8100_NECLK_SR5_TIMER0_APB 2 +#define JH8100_NECLK_SR5_TIMER0_CH0 3 +#define JH8100_NECLK_SR5_TIMER0_CH1 4 +#define JH8100_NECLK_SR5_TIMER0_CH2 5 +#define JH8100_NECLK_SR5_TIMER0_CH3 6 +#define JH8100_NECLK_SR5_TIMER1_APB 7 +#define JH8100_NECLK_SR5_TIMER1_CH0 8 +#define JH8100_NECLK_SR5_TIMER1_CH1 9 +#define JH8100_NECLK_SR5_TIMER1_CH2 10 +#define JH8100_NECLK_SR5_TIMER1_CH3 11 +#define JH8100_NECLK_USB3_CMN_SCAN_PLL 12 +#define JH8100_NECLK_USB3_CMN_SCAN_SER 13 +#define JH8100_NECLK_USB3_PIPE_IN_SCAN 14 +#define JH8100_NECLK_USB3_SCAN_PIPE 15 +#define JH8100_NECLK_USB3_SCAN_PSM 16 +#define JH8100_NECLK_USB3_SCAN_REF 17 +#define JH8100_NECLK_USB3_USB2_SCAN 18 +#define JH8100_NECLK_USB3_HSCLK 19 +#define JH8100_NECLK_USB3_HSSICLK 20 +#define JH8100_NECLK_USB3_SIECLK 21 +#define JH8100_NECLK_USB3_XCVR_SCAN_PLL 22 +#define JH8100_NECLK_USB3_XCVR_SCAN_SER 23 +#define JH8100_NECLK_USB3_TAP_TCK 24 +#define JH8100_NECLK_USB1_CMN_SCAN_PLL 25 +#define JH8100_NECLK_USB1_CMN_SCAN_SER 26 +#define JH8100_NECLK_USB1_PIPE_IN_SCAN 27 +#define JH8100_NECLK_USB1_SCAN_PIPE 28 +#define JH8100_NECLK_USB1_SCAN_PSM 29 +#define JH8100_NECLK_USB1_SCAN_REF 30 +#define JH8100_NECLK_USB1_USB2_SCAN 31 +#define JH8100_NECLK_USB1_HSCLK 32 +#define JH8100_NECLK_USB1_HSSICLK 33 +#define JH8100_NECLK_USB1_SIECLK 34 +#define JH8100_NECLK_USB1_XCVR_SCAN_PLL 35 +#define JH8100_NECLK_USB1_XCVR_SCAN_SER 36 +#define JH8100_NECLK_USB1_TAP_TCK 37 +#define JH8100_NECLK_USB2_CMN_SCAN_PLL 38 +#define JH8100_NECLK_USB2_CMN_SCAN_SER 39 +#define JH8100_NECLK_USB2_PIPE_IN_SCAN 40 +#define JH8100_NECLK_USB2_SCAN_PIPE 41 +#define JH8100_NECLK_USB2_SCAN_PSM 42 +#define JH8100_NECLK_USB2_SCAN_REF 43 +#define JH8100_NECLK_USB2_USB2_SCAN 44 +#define JH8100_NECLK_USB2_HSCLK 45 +#define JH8100_NECLK_USB2_HSSICLK 46 +#define JH8100_NECLK_USB2_SIECLK 47 +#define JH8100_NECLK_USB2_XCVR_SCAN_PLL 48 +#define JH8100_NECLK_USB2_XCVR_SCAN_SER 49 +#define JH8100_NECLK_USB2_TAP_TCK 50 +#define JH8100_NECLK_TYPEC_PIPE_DIV_SCAN 51 +#define JH8100_NECLK_TYPEC_CMN_SCAN_PLL 52 +#define JH8100_NECLK_TYPEC_CMN_SCAN_SER 53 +#define JH8100_NECLK_TYPEC_SCAN_PIPE 54 +#define JH8100_NECLK_TYPEC_SCAN_PSM 55 +#define JH8100_NECLK_TYPEC_SCAN_REF 56 +#define JH8100_NECLK_TYPEC_USB2_SCAN 57 +#define JH8100_NECLK_TYPEC_HSCLK 58 +#define JH8100_NECLK_TYPEC_HSSICLK 59 +#define JH8100_NECLK_TYPEC_SIECLK 60 +#define JH8100_NECLK_TYPEC_VID0 61 +#define JH8100_NECLK_TYPEC_VID1 62 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_PLL0 63 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_PLL1 64 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_PLL2 65 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_PLL3 66 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_SER0 67 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_SER1 68 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_SER2 69 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_SER3 70 +#define JH8100_NECLK_TYPEC_TAP_TCK 71 +#define JH8100_NECLK_VENC_AXI 72 +#define JH8100_NECLK_VC9000LE_AXI 73 +#define JH8100_NECLK_VC9000LE_APB 74 +#define JH8100_NECLK_VC9000LE_CORECLK 75 +#define JH8100_NECLK_INT_CTRL_APB 76 +#define JH8100_NECLK_PWM_8CH_APB 77 +#define JH8100_NECLK_WDT_APB 78 +#define JH8100_NECLK_WDT 79 +#define JH8100_NECLK_SPI0_APB 80 +#define JH8100_NECLK_SPI0_CORE 81 +#define JH8100_NECLK_SPI0_SCLK_IN 82 +#define JH8100_NECLK_SPI1_APB 83 +#define JH8100_NECLK_SPI1_CORE 84 +#define JH8100_NECLK_SPI1_SCLK_IN 85 +#define JH8100_NECLK_I2C0_APB 86 +#define JH8100_NECLK_I2C1_APB 87 +#define JH8100_NECLK_I2C2_APB 88 +#define JH8100_NECLK_I2C3_APB 89 +#define JH8100_NECLK_I2C4_APB 90 +#define JH8100_NECLK_I2C5_APB 91 +#define JH8100_NECLK_UART0_APB 92 +#define JH8100_NECLK_UART0_CORE 93 +#define JH8100_NECLK_UART1_CORE_PREOSC 94 +#define JH8100_NECLK_UART1_APB 95 +#define JH8100_NECLK_UART1_CORE 96 +#define JH8100_NECLK_UART2_CORE_PREOSC 97 +#define JH8100_NECLK_UART2_APB 98 +#define JH8100_NECLK_UART2_CORE 99 +#define JH8100_NECLK_UART3_CORE_PREOSC 100 +#define JH8100_NECLK_UART3_APB 101 +#define JH8100_NECLK_UART3_CORE 102 +#define JH8100_NECLK_UART4_CORE_PREOSC 103 +#define JH8100_NECLK_UART4_APB 104 +#define JH8100_NECLK_UART4_CORE 105 +#define JH8100_NECLK_I2S0_BCLK 106 +#define JH8100_NECLK_I2S0_LRCK 107 +#define JH8100_NECLK_I2S0_APB 108 +#define JH8100_NECLK_I2S0 109 +#define JH8100_NECLK_I2S0_N 110 +#define JH8100_NECLK_I2S0_BCLK_TX 111 +#define JH8100_NECLK_I2S0_LRCK_TX 112 +#define JH8100_NECLK_I2S0_BCLK_RX 113 +#define JH8100_NECLK_I2S0_LRCK_RX 114 +#define JH8100_NECLK_I2S1_BCLK 115 +#define JH8100_NECLK_I2S1_LRCK 116 +#define JH8100_NECLK_I2S1_APB 117 +#define JH8100_NECLK_I2S1 118 +#define JH8100_NECLK_I2S1_N 119 +#define JH8100_NECLK_I2S1_BCLK_TX 120 +#define JH8100_NECLK_I2S1_LRCK_TX 121 +#define JH8100_NECLK_I2S1_BCLK_RX 122 +#define JH8100_NECLK_I2S1_LRCK_RX 123 +#define JH8100_NECLK_I2S2_BCLK 124 +#define JH8100_NECLK_I2S2_LRCK 125 +#define JH8100_NECLK_I2S2_APB 126 +#define JH8100_NECLK_I2S2 127 +#define JH8100_NECLK_I2S2_N 128 +#define JH8100_NECLK_I2S2_BCLK_TX 129 +#define JH8100_NECLK_I2S2_LRCK_TX 130 +#define JH8100_NECLK_I2S2_BCLK_RX 131 +#define JH8100_NECLK_I2S2_LRCK_RX 132 +#define JH8100_NECLK_I2S3_BCLK 133 +#define JH8100_NECLK_I2S3_LRCK 134 +#define JH8100_NECLK_I2S0_STEREO_APB 135 +#define JH8100_NECLK_I2S0_STEREO 136 +#define JH8100_NECLK_I2S0_STEREO_N 137 +#define JH8100_NECLK_I2S0_STEREO_BCLK_TX 138 +#define JH8100_NECLK_I2S0_STEREO_LRCK_TX 139 +#define JH8100_NECLK_I2S0_STEREO_BCLK_RX_ICG 140 +#define JH8100_NECLK_I2S0_STEREO_LRCK_RX 141 +#define JH8100_NECLK_PDM_4MIC_DMIC 142 +#define JH8100_NECLK_PDM_4MIC_APB 143 +#define JH8100_NECLK_PDM_4MIC_SCAN 144 +#define JH8100_NECLK_CAN0_CTRL_PCLK 145 +#define JH8100_NECLK_CAN0_CTRL 146 +#define JH8100_NECLK_CAN0_CTRL_TIMER 147 +#define JH8100_NECLK_CAN1_CTRL_PCLK 148 +#define JH8100_NECLK_CAN1_CTRL 149 +#define JH8100_NECLK_CAN1_CTRL_TIMER 150 +#define JH8100_NECLK_SMBUS0_APB 151 +#define JH8100_NECLK_SMBUS0_CORE 152 +#define JH8100_NECLK_IOMUX_EAST_PCLK 153 +#define JH8100_NECLK_USB3_ICG_EN 154 +#define JH8100_NECLK_USB1_ICG_EN 155 +#define JH8100_NECLK_USB2_ICG_EN 156 +#define JH8100_NECLK_USBC_ICG_EN 157 +#define JH8100_NECLK_VENC_ICG_EN 158 +#define JH8100_NECLK_WDT0_ICG_EN 159 +#define JH8100_NECLK_SPI0_ICG_EN 160 +#define JH8100_NECLK_SPI1_ICG_EN 161 +#define JH8100_NECLK_UART0_ICG_EN 162 +#define JH8100_NECLK_UART1_ICG_EN 163 +#define JH8100_NECLK_UART2_ICG_EN 164 +#define JH8100_NECLK_UART3_ICG_EN 165 +#define JH8100_NECLK_UART4_ICG_EN 166 +#define JH8100_NECLK_I2S0_ICG_EN 167 +#define JH8100_NECLK_I2S1_ICG_EN 168 +#define JH8100_NECLK_I2S2_ICG_EN 169 +#define JH8100_NECLK_I2S_STEREO_ICG_EN 170 +#define JH8100_NECLK_PDM_4MIC_ICG_EN 171 +#define JH8100_NECLK_CAN0_ICG_EN 172 +#define JH8100_NECLK_CAN1_ICG_EN 173 +#define JH8100_NECLK_SMBUS0_ICG_EN 174 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index b25f6522f3d4..30a99c78341a 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -32,4 +32,63 @@ #define JH8100_NWRST_MERAK0_TVSENSOR 8 #define JH8100_NWRST_MERAK1_TVSENSOR 9 +/* + * NECRG resets: assert0 + */ +#define JH8100_NERST_PRESETN 0 +#define JH8100_NERST_USB3_APB 1 +#define JH8100_NERST_USB3_TORR_PHY 2 +#define JH8100_NERST_USB3_CONFIG 3 +#define JH8100_NERST_USB1_APB 4 +#define JH8100_NERST_USB1_TORRENT_PHY 5 +#define JH8100_NERST_USB1_CONFIG 6 +#define JH8100_NERST_USB2_APB 7 +#define JH8100_NERST_USB2_TORRENT_PHY 8 +#define JH8100_NERST_USB2_CONFIG 9 +#define JH8100_NERST_USBC_APB 10 +#define JH8100_NERST_USBC_CONFIG 11 +#define JH8100_NERST_VC9000LE 12 +#define JH8100_NERST_INT_CTRL_APB 13 +#define JH8100_NERST_PWM_8CH_APB 14 +#define JH8100_NERST_WDT0 15 +#define JH8100_NERST_SPI0 16 +#define JH8100_NERST_SPI1 17 +#define JH8100_NERST_I2C0 18 +#define JH8100_NERST_I2C1 19 +#define JH8100_NERST_I2C2 20 +#define JH8100_NERST_I2C3 21 +#define JH8100_NERST_I2C4 22 +#define JH8100_NERST_I2C5 23 +#define JH8100_NERST_UART0 24 +#define JH8100_NERST_UART1 25 +#define JH8100_NERST_UART2 26 +#define JH8100_NERST_UART3 27 +#define JH8100_NERST_UART4 28 +#define JH8100_NERST_MAILBOX_PRESETN 29 +#define JH8100_NERST_TIMER0_APB 30 +#define JH8100_NERST_TIMER0_CH0 31 + +/* + * NECRG resets: assert1 + */ + +#define JH8100_NERST_TIMER0_CH1 32 +#define JH8100_NERST_TIMER0_CH2 33 +#define JH8100_NERST_TIMER0_CH3 34 +#define JH8100_NERST_TIMER1_APB 35 +#define JH8100_NERST_TIMER1_CH0 36 +#define JH8100_NERST_TIMER1_CH1 37 +#define JH8100_NERST_TIMER1_CH2 38 +#define JH8100_NERST_TIMER1_CH3 39 +#define JH8100_NERST_I2S0_RSTN_APB 40 +#define JH8100_NERST_I2S1_RSTN_APB 41 +#define JH8100_NERST_I2S2_RSTN_APB 42 +#define JH8100_NERST_I2S0_STEREO_APB 43 +#define JH8100_NERST_PDM 44 +#define JH8100_NERST_CAN0 45 +#define JH8100_NERST_CAN1 46 +#define JH8100_NERST_SMBUS0 47 +#define JH8100_NERST_SYS_IOMUX_E 48 +#define JH8100_NERST_DUBHE_TVSENSOR 49 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 1880186 Return-Path: X-Original-To: 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(CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:15 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:09 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 11/16] dt-bindings: clock: Add StarFive JH8100 South-West clock and reset generator Date: Tue, 26 Dec 2023 13:38:43 +0800 Message-ID: <20231226053848.25089-12-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the South-West clock and reset generator (SWCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/starfive,jh8100-swcrg.yaml | 64 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 12 ++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 8 +++ 3 files changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml new file mode 100644 index 000000000000..287dff7e91e3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-swcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 South-West Clock And Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-swcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: APB_BUS clock from SYSCRG + - description: VDEC_ROOT clock from SYSCRG + - description: FLEXNOC1 clock from SYSCRG + + clock-names: + items: + - const: apb_bus + - const: vdec_root + - const: flexnoc1 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@12720000 { + compatible = "starfive,jh8100-swcrg"; + reg = <0x12720000 0x10000>; + clocks = <&syscrg JH8100_SYSCLK_APB_BUS>, + <&syscrg JH8100_SYSCLK_VDEC_ROOT>, + <&syscrg JH8100_SYSCLK_FLEXNOC1>; + clock-names = "apb_bus", "vdec_root", "flexnoc1"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index c37b42f3eacd..7b337c1495be 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -339,4 +339,16 @@ #define JH8100_NECLK_CAN1_ICG_EN 173 #define JH8100_NECLK_SMBUS0_ICG_EN 174 +/* SWCRG clocks */ +#define JH8100_SWCLK_JPEG_AXI 0 +#define JH8100_SWCLK_VC9000DJ_AXI 1 +#define JH8100_SWCLK_VC9000DJ_VDEC 2 +#define JH8100_SWCLK_VC9000DJ_APB 3 +#define JH8100_SWCLK_VDEC_AXI 4 +#define JH8100_SWCLK_VC9000D_AXI 5 +#define JH8100_SWCLK_VC9000D_VDEC 6 +#define JH8100_SWCLK_VC9000D_APB 7 +#define JH8100_SWCLK_JPEG_ICG_EN 8 +#define JH8100_SWCLK_VDEC_ICG_EN 9 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index 30a99c78341a..de4f25dc301d 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -91,4 +91,12 @@ #define JH8100_NERST_SYS_IOMUX_E 48 #define JH8100_NERST_DUBHE_TVSENSOR 49 +/* + * SWCRG resets: assert0 + */ +#define JH8100_SWRST_PRESETN 0 +#define JH8100_SWRST_VC9000DJ 1 +#define JH8100_SWRST_VC9000D 2 +#define JH8100_SWRST_DDR_TVSENSOR 3 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 1880187 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=147.75.80.249; helo=am.mirrors.kernel.org; envelope-from=devicetree+bounces-28443-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [147.75.80.249]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SzkG14LyJz20RL for ; Tue, 26 Dec 2023 16:43:21 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 5A6CF1F2272B for ; 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Tue, 26 Dec 2023 13:40:28 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:22 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator Date: Tue, 26 Dec 2023 13:38:45 +0800 Message-ID: <20231226053848.25089-14-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the Always-On clock and reset generator (AONCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Reviewed-by: Krzysztof Kozlowski --- .../clock/starfive,jh8100-aoncrg.yaml | 74 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 67 +++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 16 ++++ 3 files changed, 157 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml new file mode 100644 index 000000000000..4ae1ef827fc9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 Always-On Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-aoncrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII func + - description: GMAC0 RGMII func + - description: AON 125MHz clock + - description: AON 2000MHz clock + - description: AON 200MHz clock + - description: AON 667MHz clock + - description: RTC clock + + clock-names: + items: + - const: osc + - const: gmac0-rmii-func + - const: gmac0-rgmii-func + - const: aon125 + - const: aon2000 + - const: aon200 + - const: aon667 + - const: rtc + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1f310000 { + compatible = "starfive,jh8100-aoncrg"; + reg = <0x1f310000 0x10000>; + clocks = <&osc>, <&gmac0_rmii_func>, <&gmac0_rgmii_func>, <&aon125>, + <&aon2000>, <&aon200>, <&aon667>, <&rtc>; + clock-names = "osc", "gmac0-rmii-func", "gmac0-rgmii-func", "aon125", + "aon2000", "aon200", "aon667", "rtc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index 7b337c1495be..8207d5a2f4b3 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -351,4 +351,71 @@ #define JH8100_SWCLK_JPEG_ICG_EN 8 #define JH8100_SWCLK_VDEC_ICG_EN 9 +/* AONCRG clocks */ +#define JH8100_AONCLK_GMAC0_RMII_REFIN 0 +#define JH8100_AONCLK_GMAC0_RGMII_RXIN 1 +#define JH8100_AONCLK_GMAC0_GTXCLK 2 +#define JH8100_AONCLK_AON_1000 3 +#define JH8100_AONCLK_AON_400 4 +#define JH8100_AONCLK_AON_400_POSTOSC 5 +#define JH8100_AONCLK_AON_500 6 +#define JH8100_AONCLK_AON_500_POSTOSC 7 +#define JH8100_AONCLK_XSPI_PHY 8 +#define JH8100_AONCLK_AON_100 9 +#define JH8100_AONCLK_AON_100_POSTOSC 10 +#define JH8100_AONCLK_AON_50_POSTOSC 11 +#define JH8100_AONCLK_DDR50_POSTOCC_ICG 12 +#define JH8100_AONCLK_DDR100_POSTOCC_ICG 13 +#define JH8100_AONCLK_PUFRT_APB 14 +#define JH8100_AONCLK_RTC_HMS_APB 15 +#define JH8100_AONCLK_RTC_INTERNAL 16 +#define JH8100_AONCLK_RTC_HMS_OSC32K 17 +#define JH8100_AONCLK_RTC_HMS_CAL 18 +#define JH8100_AONCLK_GMAC0_AXI128_AHB 19 +#define JH8100_AONCLK_GMAC0_AXI128_MSTRCLK 20 +#define JH8100_AONCLK_GMAC0_AXI128_AXI 21 +#define JH8100_AONCLK_GMAC0_RMII_RTX 22 +#define JH8100_AONCLK_GMAC0_AXI128_TX 23 +#define JH8100_AONCLK_GMAC0_AXI128_TX_INV 24 +#define JH8100_AONCLK_GMAC0_AXI128_RX 25 +#define JH8100_AONCLK_GMAC0_AXI128_RX_INV 26 +#define JH8100_AONCLK_GMAC0_GTXC 27 +#define JH8100_AONCLK_XSPI_AXI 28 +#define JH8100_AONCLK_XSPI_APB 29 +#define JH8100_AONCLK_XSPI_XSPI_PHY 30 +#define JH8100_AONCLK_TVSENSOR_PCLK 31 +#define JH8100_AONCLK_TVSENSOR_TSADC 32 +#define JH8100_AONCLK_TVSENSOR_BG 33 +#define JH8100_AONCLK_MEU_PCLK_AP 34 +#define JH8100_AONCLK_MEU_PCLK_SCP 35 +#define JH8100_AONCLK_MEU_MEM_AXI 36 +#define JH8100_AONCLK_AXIMEM_128B_ACLK 37 +#define JH8100_AONCLK_APB2BISR_APB 38 +#define JH8100_AONCLK_APB2BISR_BISR 39 +#define JH8100_AONCLK_EMMC_S_PCLK 40 +#define JH8100_AONCLK_EMMC_MSTRCLK 41 +#define JH8100_AONCLK_EMMC 42 +#define JH8100_AONCLK_EMMC_SDMCLK 43 +#define JH8100_AONCLK_EMMC_SDPHY_PCLK 44 +#define JH8100_AONCLK_SDIO0_PCLK 45 +#define JH8100_AONCLK_SDIO0_MSTRCLK 46 +#define JH8100_AONCLK_SDIO0 47 +#define JH8100_AONCLK_SDIO0_SDMCLK 48 +#define JH8100_AONCLK_SDIO0_SDPHY_PCLK 49 +#define JH8100_AONCLK_HCLK 50 +#define JH8100_AONCLK_ACLK 51 +#define JH8100_AONCLK_PERF_MSTRCLK 52 +#define JH8100_AONCLK_PERF_SLVCLK 53 +#define JH8100_AONCLK_GCLK0 54 +#define JH8100_AONCLK_GCLK_OSC 55 +#define JH8100_AONCLK_RTC_ICG_EN 56 +#define JH8100_AONCLK_GMAC0_ICG_EN 57 +#define JH8100_AONCLK_XSPI_ICG_EN 58 +#define JH8100_AONCLK_TVSENSOR0_ICG_EN 59 +#define JH8100_AONCLK_MEU_ICG_EN 60 +#define JH8100_AONCLK_APB2BISR_ICG_EN 61 +#define JH8100_AONCLK_EMMC_ICG_EN 62 +#define JH8100_AONCLK_SDIO0_ICG_EN 63 +#define JH8100_AONCLK_TOP_ICG_EN 64 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index de4f25dc301d..23f15d4be22f 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -99,4 +99,20 @@ #define JH8100_SWRST_VC9000D 2 #define JH8100_SWRST_DDR_TVSENSOR 3 +/* + * AONCRG resets: assert0 + */ +#define JH8100_AONRST_AON_IOMUX_PRESETN 0 +#define JH8100_AONRST_RTC 1 +#define JH8100_AONRST_GMAC0 2 +#define JH8100_AONRST_XSPI 3 +#define JH8100_AONRST_TVSENSOR 4 +#define JH8100_AONRST_MEU 5 +#define JH8100_AONRST_AXIMEM_128B_ARESET 6 +#define JH8100_AONRST_DFT_APB2BISR_APB 7 +#define JH8100_AONRST_SDIO0 8 +#define JH8100_AONRST_EMMC 9 +#define JH8100_AONRST_TOP 10 +#define JH8100_AONRST_IRQ_CTRL 11 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */