diff mbox series

[2/2] arch/riscv: Added support for RISC-V vector extension on the architecture menu.

Message ID CAF2ART_=XUWL8bgtdV7vUgz5SQJXVyBAAS0ixcYLVbaaA++_4w@mail.gmail.com
State Superseded
Headers show
Series [1/2] package/llvm: Support for RISC-V on the LLVM package | expand

Commit Message

Abel Bernabeu July 3, 2022, 11:26 p.m. UTC 
From d8f288513e88cfb7f78f090ad0c02e6122a99097 Mon Sep 17 00:00:00 2001
From: Abel Bernabeu <abel@x-silicon.com>
Date: Mon, 4 Jul 2022 00:41:09 +0200
Subject: [PATCH 2/2] arch/riscv: Added support for RISC-V vector extension
on
 the architecture menu.

This new setting will allow to test new toolchains already available
that support the vector extension (more patches coming soon).
---
 arch/Config.in.riscv | 7 +++++++
 arch/arch.mk.riscv   | 4 ++++
 2 files changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 288ed833eb..e4dc936cf8 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -18,6 +18,9 @@  config BR2_RISCV_ISA_RVD
 config BR2_RISCV_ISA_RVC
        bool

+config BR2_RISCV_ISA_RVV
+       bool
+
 choice
        prompt "Target Architecture Variant"
        default BR2_riscv_g
@@ -63,6 +66,10 @@  config BR2_RISCV_ISA_CUSTOM_RVD
 config BR2_RISCV_ISA_CUSTOM_RVC
        bool "Compressed Instructions (C)"
        select BR2_RISCV_ISA_RVC
+
+config BR2_RISCV_ISA_CUSTOM_RVV
+       bool "Vector Instructions (V)"
+       select BR2_RISCV_ISA_RVV
 endif

 choice
diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index f3bf2b3467..07a94aa6a4 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -26,5 +26,9 @@  endif
 ifeq ($(BR2_RISCV_ISA_RVC),y)
 GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
 endif
+ifeq ($(BR2_RISCV_ISA_RVV),y)
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
+endif
+

 endif