| Message ID | 20230815100600.297932-2-jamie.gibbons@microchip.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Update RISC-V Instruction Sets | expand |
On Tue, 15 Aug 2023 11:05:58 +0100 Jamie Gibbons via buildroot <buildroot@buildroot.org> wrote: > +if BR2_riscv_g > + > +comment "Instruction Set Extensions" > + > +config BR2_RISCV_ISA_CUSTOM_RVC > + bool "Compressed Instructions (C)" > + select BR2_RISCV_ISA_RVC > + > +config BR2_RISCV_ISA_CUSTOM_RVV > + bool "Vector Instructions (V)" > + select BR2_RISCV_ISA_RVV > + select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 > + > +endif I believe this is still not correct: now those options are only available for the BR2_riscv_g case, no longer for the custom RISC-V core case. Those two options should be available both as add-ons for the riscv_g *and* for the riscv custom cases. Best regards, Thomas
Hi Thomas, On Tue, 2023-08-15 at 21:38 +0200, Thomas Petazzoni wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On Tue, 15 Aug 2023 11:05:58 +0100 > Jamie Gibbons via buildroot <buildroot@buildroot.org> wrote: > > > +if BR2_riscv_g > > + > > +comment "Instruction Set Extensions" > > + > > +config BR2_RISCV_ISA_CUSTOM_RVC > > + bool "Compressed Instructions (C)" > > + select BR2_RISCV_ISA_RVC > > + > > +config BR2_RISCV_ISA_CUSTOM_RVV > > + bool "Vector Instructions (V)" > > + select BR2_RISCV_ISA_RVV > > + select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 > > + > > +endif > > I believe this is still not correct: now those options are only > available for the BR2_riscv_g case, no longer for the custom RISC-V > core case. > > Those two options should be available both as add-ons for the riscv_g > *and* for the riscv custom cases. > Apologies, I misunderstood your suggestion to "move" the options. I will update this and send a v2. Regards, Jamie.
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 3dfbb4165f..ab839fd8a4 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -35,6 +35,21 @@ config BR2_riscv_g help General purpose (G) is equivalent to IMAFD. +if BR2_riscv_g + +comment "Instruction Set Extensions" + +config BR2_RISCV_ISA_CUSTOM_RVC + bool "Compressed Instructions (C)" + select BR2_RISCV_ISA_RVC + +config BR2_RISCV_ISA_CUSTOM_RVV + bool "Vector Instructions (V)" + select BR2_RISCV_ISA_RVV + select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 + +endif + config BR2_riscv_custom bool "Custom architecture" select BR2_RISCV_ISA_RVI @@ -62,15 +77,6 @@ config BR2_RISCV_ISA_CUSTOM_RVD depends on BR2_RISCV_ISA_RVF select BR2_RISCV_ISA_RVD -config BR2_RISCV_ISA_CUSTOM_RVC - bool "Compressed Instructions (C)" - select BR2_RISCV_ISA_RVC - -config BR2_RISCV_ISA_CUSTOM_RVV - bool "Vector Instructions (V)" - select BR2_RISCV_ISA_RVV - select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 - endif choice
Allow a RISC-V G core to support C and V. Move custom RVC and RVV instructions from RISC-V custom core to RISC-V general core. Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> --- arch/Config.in.riscv | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-)