| Message ID | 20230815054327.1436-1-peterlin@andestech.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v2] configs/andes_ae350_45: Select RVA for AE350 platform | expand |
Hello, On Tue, 15 Aug 2023 13:43:27 +0800 Yu Chien Peter Lin <peterlin@andestech.com> wrote: > Let's select the RVA as Andes 45-series CPUs support > IMAFDC extensions. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v1 -> v2: > - reword commit message > --- > configs/andes_ae350_45_defconfig | 1 + > 1 file changed, 1 insertion(+) Applied to next, thanks. However, it could be simplified a bit thanks to recent changes in the RISC-V support. We could have: @@ -1,9 +1,4 @@ BR2_riscv=y -BR2_riscv_custom=y -BR2_RISCV_ISA_RVM=y -BR2_RISCV_ISA_RVA=y -BR2_RISCV_ISA_RVF=y -BR2_RISCV_ISA_RVD=y BR2_RISCV_ISA_RVC=y BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_0=y BR2_GLOBAL_PATCH_DIR="board/andes/ae350/patches" Indeed, now riscv_g still allows to enable the C extension. Could you have a look into this and submit a patch? Thanks a lot! Thomas
diff --git a/configs/andes_ae350_45_defconfig b/configs/andes_ae350_45_defconfig index 998276635b..7e606444c0 100644 --- a/configs/andes_ae350_45_defconfig +++ b/configs/andes_ae350_45_defconfig @@ -1,6 +1,7 @@ BR2_riscv=y BR2_riscv_custom=y BR2_RISCV_ISA_CUSTOM_RVM=y +BR2_RISCV_ISA_CUSTOM_RVA=y BR2_RISCV_ISA_CUSTOM_RVF=y BR2_RISCV_ISA_CUSTOM_RVD=y BR2_RISCV_ISA_CUSTOM_RVC=y
Let's select the RVA as Andes 45-series CPUs support IMAFDC extensions. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> --- Changes v1 -> v2: - reword commit message --- configs/andes_ae350_45_defconfig | 1 + 1 file changed, 1 insertion(+)