diff mbox series

[U-Boot,v3,16/28] riscv: align mtvec on a 4-byte boundary

Message ID	20181109125923.7034-17-lukas.auer@aisec.fraunhofer.de
State	Superseded
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> To: <u-boot@lists.denx.de> Date: Fri, 9 Nov 2018 13:59:11 +0100 Message-ID: <20181109125923.7034-17-lukas.auer@aisec.fraunhofer.de> In-Reply-To: <20181109125923.7034-1-lukas.auer@aisec.fraunhofer.de> References: <20181109125923.7034-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 Cc: Greentime Hu <green.hu@gmail.com> Subject: [U-Boot] [PATCH v3 16/28] riscv: align mtvec on a 4-byte boundary Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	General fixes / cleanup for RISC-V and improvements to qemu-riscv \| expand [U-Boot,v3,00/28] General fixes / cleanup for RISC-V and improvements to qemu-riscv [U-Boot,v3,01/28] tools: .gitignore: add prelink-riscv [U-Boot,v3,02/28] dts: riscv: update makefile to also clean the RISC-V dts directory [U-Boot,v3,03/28] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I [U-Boot,v3,04/28] riscv: select CONFIG_PHYS_64BIT on RV64I systems [U-Boot,v3,05/28] riscv: add Kconfig entries for the C and A ISA extensions [U-Boot,v3,06/28] riscv: set -march and -mabi based on the Kconfig configuration [U-Boot,v3,07/28] riscv: enable -fdata-sections [U-Boot,v3,08/28] riscv: fix use of incorrectly sized variables [U-Boot,v3,09/28] riscv: make use of the barrier functions from Linux [U-Boot,v3,10/28] riscv: do not reimplement generic io functions [U-Boot,v3,11/28] riscv: complete the list of exception codes [U-Boot,v3,12/28] riscv: treat undefined exception codes as reserved [U-Boot,v3,13/28] riscv: hang on unhandled exceptions [U-Boot,v3,14/28] riscv: implement the invalidate_icache_* functions [U-Boot,v3,15/28] riscv: fix inconsistent use of spaces and tabs in start.S [U-Boot,v3,16/28] riscv: align mtvec on a 4-byte boundary [U-Boot,v3,17/28] Drop CONFIG_INIT_CRITICAL [U-Boot,v3,18/28] riscv: remove unused labels in start.S [U-Boot,v3,19/28] riscv: do not blindly modify the mstatus CSR [U-Boot,v3,20/28] riscv: save hart ID and device tree passed by prior boot stage [U-Boot,v3,21/28] riscv: qemu: use device tree passed by prior boot stage [U-Boot,v3,22/28] riscv: qemu: support booting Linux [U-Boot,v3,23/28] riscv: align bootm implementation with that of other architectures [U-Boot,v3,24/28] distro_bootcmd: add VirtIO distro boot command [U-Boot,v3,25/28] riscv: qemu: enable distro boot [U-Boot,v3,26/28] dm: core: add missing prototype for ofnode_read_u64 [U-Boot,v3,27/28] riscv: qemu: detect and boot the kernel passed by QEMU [U-Boot,v3,28/28] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL

Commit Message

Lukas Auer Nov. 9, 2018, 12:59 p.m. UTC

The machine trap-vector base address (mtvec) must be aligned on a 4-byte
boundary. Add the necessary align directive to trap_entry.

This patch also removes the global directive for trap_entry, which is
not required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/riscv/cpu/start.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bd5904500c..88b4aaa1c0 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -42,7 +42,6 @@  nmi_vector:
 trap_vector:
 	j	trap_entry
 
-.global trap_entry
 handle_reset:
 	li	t0, CONFIG_SYS_SDRAM_BASE
 	SREG	a2, 0(t0)
@@ -208,6 +207,7 @@  call_board_init_r:
 /*
  * trap entry
  */
+.align 2
 trap_entry:
 	addi	sp, sp, -32*REGBYTES
 	SREG	x1, 1*REGBYTES(sp)