@@ -16,6 +16,7 @@ config TARGET_MICROBLAZE_GENERIC
select DM
select DM_SERIAL
select ENV_IS_IN_FLASH
+ select SYSRESET
endchoice
@@ -47,3 +47,11 @@ int spl_start_uboot(void)
return 1;
}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ __asm__ __volatile__ ("mts rmsr, r0;" \
+ "bra r0");
+
+ return 0;
+}
@@ -1,14 +1 @@
-#ifndef _ASM_MICROBLAZE_GPIO_H_
-#define _ASM_MICROBLAZE_GPIO_H_
-
#include <asm-generic/gpio.h>
-
-/* Allocation functions */
-extern int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0,
- u32 gpio_no1);
-extern int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no);
-
-#define gpio_status() gpio_info()
-extern void gpio_info(void);
-
-#endif
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2007 Michal Simek
+ * (C) Copyright 2007-2018 Michal Simek
*
- * Michal SIMEK <monstr@monstr.eu>
+ * Michal SIMEK <monstr@monstr.eu>
*/
/*
@@ -12,6 +12,8 @@
#include <common.h>
#include <config.h>
+#include <dm.h>
+#include <dm/lists.h>
#include <fdtdec.h>
#include <asm/processor.h>
#include <asm/microblaze_intc.h>
@@ -22,10 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_XILINX_GPIO
-static int reset_pin = -1;
-#endif
-
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
static struct udevice *watchdog_dev;
#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
@@ -66,33 +64,6 @@ int dram_init(void)
return 0;
};
-#if !defined(CONFIG_SYSRESET) || defined(CONFIG_SPL_BUILD)
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_XILINX_GPIO
- if (reset_pin != -1)
- gpio_direction_output(reset_pin, 1);
-#endif
-#endif
- puts("Resetting board\n");
- __asm__ __volatile__ (" mts rmsr, r0;" \
- "bra r0");
-
- return 0;
-}
-#endif
-
-static int gpio_init(void)
-{
-#ifdef CONFIG_XILINX_GPIO
- reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
- if (reset_pin != -1)
- gpio_request(reset_pin, "reset_pin");
-#endif
- return 0;
-}
-
#ifdef CONFIG_WDT
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
@@ -117,8 +88,6 @@ void watchdog_reset(void)
int board_late_init(void)
{
- gpio_init();
-
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
watchdog_dev = NULL;
@@ -133,6 +102,13 @@ int board_late_init(void)
wdt_start(watchdog_dev, 0, 0);
puts("Watchdog: Started\n");
#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE)
+ int ret;
+ ret = device_bind_driver(gd->dm_root, "mb_soft_reset",
+ "reset_soft", NULL);
+ if (ret)
+ printf("Warning: No reset driver: ret=%d\n", ret);
+#endif
return 0;
}
@@ -13,9 +13,6 @@
/* Microblaze is microblaze_0 */
#define XILINX_FSL_NUMBER 3
-/* GPIO is LEDs_4Bit*/
-#define XILINX_GPIO_BASEADDR 0x40000000
-
/* Flash Memory is FLASH_2Mx32 */
#define XILINX_FLASH_START 0x2c000000
#define XILINX_FLASH_SIZE 0x00800000
@@ -39,6 +39,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
CONFIG_XILINX_GPIO=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHY_ATHEROS=y
@@ -56,5 +57,7 @@ CONFIG_XILINX_AXIEMAC=y
CONFIG_XILINX_EMACLITE=y
CONFIG_SYS_NS16550=y
CONFIG_XILINX_UARTLITE=y
+CONFIG_SYSRESET_GPIO=y
+CONFIG_SYSRESET_MICROBLAZE=y
CONFIG_WDT=y
CONFIG_XILINX_TB_WATCHDOG=y
@@ -185,6 +185,7 @@ config SANDBOX_GPIO_COUNT
config XILINX_GPIO
bool "Xilinx GPIO driver"
+ depends on DM_GPIO
help
This config enable the Xilinx GPIO driver for Microblaze.
@@ -38,11 +38,6 @@
/* setting reset address */
/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
-/* gpio */
-#ifdef XILINX_GPIO_BASEADDR
-# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
-#endif
-
#define CONFIG_SYS_MALLOC_LEN 0xC0000
/* Stack location before relocation */
Converting GPIO to DM requires to do changes in reset subsystem that's why support for Microblaze soft reset via sysreset and GPIO sysreset support was added. These two patches enables enabling GPIO DM. Microblaze soft reset is bind at last reset method. GPIO reset is handled via sysreset with adding this fragment to DT. gpio-restart { compatible = "gpio-restart"; gpios = <&reset_gpio 0 0 0>; /* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */ }; hard-reset-gpio property is not documented and also handled. Conversion is required. Unfortunately do_reset is required for SPL that's why use only soft microblaze reset for now. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- This patch depends on: https://lists.denx.de/pipermail/u-boot/2018-July/334459.html https://lists.denx.de/pipermail/u-boot/2018-July/334460.html https://lists.denx.de/pipermail/u-boot/2018-July/334549.html https://lists.denx.de/pipermail/u-boot/2018-July/334647.html --- arch/microblaze/Kconfig | 1 + arch/microblaze/cpu/spl.c | 8 ++++ arch/microblaze/include/asm/gpio.h | 13 ------ .../xilinx/microblaze-generic/microblaze-generic.c | 46 ++++++---------------- board/xilinx/microblaze-generic/xparameters.h | 3 -- configs/microblaze-generic_defconfig | 3 ++ drivers/gpio/Kconfig | 1 + include/configs/microblaze-generic.h | 5 --- 8 files changed, 24 insertions(+), 56 deletions(-)